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fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
fifo-verilog
- 自己设计的一种FIFO寄存器，用verilog 编写，QUARTUS II下验证-Own design of a FIFO register, with verilog preparation, QUARTUS II certification under
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
LVDS
- 高速串行差分接口（HSDI）设计实例,用QUARTUS和利用FPGA实现LVDS的方法。-High-speed serial differential interfaces (HSDI) design example implementation using FPGA LVDS QUARTUS and use of the method.
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
FIR
- Quartus II中滤波器的设计，里面含有高通滤波器，低通滤波器，带阻滤波器，主要用于滤除心电信号中的干扰-Quartus II filter design, which contains a high-pass filter, low-pass filter, band stop filter, mainly used for filtering of ECG signal interference
PS_2
- 此模块用于"PS/2接口的鼠标或键盘"与"具有外部读写的8位并口单片机"双向通信模块. Verilog HDL语言编写,在Quartus II 8.1 (32-Bit)软件中编译,并下载至EPM7128SLC84-10芯片中通过. 文件中有详细的注解. 此模块具有对于PS/2时钟和数据线的滤波功能,这样减少外部干扰，保证通信的可靠性！ -This module for the "PS/2 mouse or keyboard interface" and "read
horse_light4
- 六种花样的流水灯，从左至右，从右至左，中间向两边，两边向中间，跳格闪烁等。verilog语言编写； 并且扩展容易； 有两个状态机构成实现。quartus 9.0和7.1仿真通过。无错误，无警告。-Six kinds of patterns of flowing water lights, from left to right, from right to left, in the middle to both sides, both sides toward the middle, ju
CDM2.04.16WHQLCertified
- altera quartus 9.0 在win7 64位下的下载器驱动-altera quartus 9.0 usb_byteblaster_driver in window7 64
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
Crack_QII70
- Quartus II 7.0 crack
QII-7.2-crack
- 常用的quartus软件 7.2版本 破解文件 -Commonly used software version 7.2 crack file quartus
4
- QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the
5
- vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2
matlab_quartus
- 可以方便地将matlab里的数据导入quartus中的波形仿真文件中，很有用-Matlab can easily import the data in waveform simulation Quartus document, very useful
Quartusguide_huawei_pdf[1]
- quartus中文全部说明 可以方便初学者使用 改软件-Quartus Chinese full descr iption can be easily changed to use software for beginners
200681556499797
- 曼彻斯特编解码 用vhdl编写的，经过quartus功能仿真测试过了的-Manchester codec prepared using VHDL, the Quartus functional simulation has been tested