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HardCamera
- The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
RS232capture
- This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file
stackfiles
- VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower la
dds_easy
- 直接频率合成DDS模块的ise工程,可以直接下载,在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波,也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位,可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram,为节省储存空间仅需要储存1/4周期的数据。根据需要,可以重新修改数据,改变波形。-DDS direct frequency synthesizer module ,ise project, can be dir
TESTRAM
- FPGA,双口RAM测试程序,仿真双口RAM工作时序,对时序的理解!适合对双口RAM不太了解的初学者使用!QUARTUSII8.0软件平台仿真通过!-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much
TechXclusives-ReconfiguringBlockRAMs
- Xilinx FPGA block RAM reconfig via JTAG
VHDL
- 双口RAM模块源代码(VHDL),用于开发FPGA的双口RAM,可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
x3cs400_uart
- 基于X3cS400的串口通讯程序,开发环境ISE7.0,使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA, develop enviroment: ISE7.0,completed by verilog。 The result could be seen on the Uart debug assitant.
jj
- 本题设计一个数字存储示波器,以Xilinx公司20万门FPGA芯片为核心,辅以必要的外围电路(包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块),利用VHDL语言编程,实现了任意波形的单次触发、连续触发和存储回放功能,并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时,将外部输入信号经信号调理模块调节到A/D电路输入范围,经A/D转换后送入FPGA内部的双口RAM进行高速缓存,并将结果通过D/A转换送给通用示波器进行显示,完成了对中、低频信号的实时采样和高频信号的等效采
FIFO
- 设计了一个具有双时钟信号,双复位信号的FIFO,用于FPGA中的数据缓冲,RAM的定义是参数型,可以根据自己的需求,修改此参数,完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
430MENUN_fpga_RAOM_LCD_KEY4X4
- msp430和fpga通信程序,可以实现单片机对fpga的通信430对fpga——ram的读写。程序包括两部分:msp430程序 和fpga程序,只需要将程序下载到fpga 和 单片机即可-fpga msp430 and communication procedures, can achieve single chip communications on 430 pairs of fpga fpga- ram read and write. Program consists of two par
The_dual-port_RAM-based_FPGA
- 基于FPGA的双口RAM实现及应用,对RAM有一个系统的介绍-The dual-port RAM-based FPGA Implementation and Application of RAM to have a systematic introduction
ram
- 用VHDL描述了RAM的读写,很好的一个小东东,要你好好学习,用于开发RAM-OK,OK,VHDL ,FPGA,RAM,WRITE AND READ ,YOU WILL LIKE IT,ARE YOU?
Two_port_RAMa
- Mactel公司的TWO PORT RAM的详细使用指南,通过具体的实例,解释的特别清楚,对于使用actel公司的fpga芯片来说帮助很大!-TWO PORT RAM Mactel' s detailed user guide, through specific examples to explain the particularly clear, for use actel fpga chip company is very helpful!
rec
- 双口ram的写入程序,用于fpga,测试通过-ram' s written procedures
blk_write
- verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
ad-ram
- ad采样 通过fpga 传输给ram-ad fpga ram verilog
shishi
- 基于FPGA的实时采样系统设计!双口ram典型应用!-FPGA-based real-time sampling system!
equivalent_sample
- 基于FPGA的等效采样系统设计,包含状态机设计,双口ram使用方法,分频设计等-FPGA-based equivalent sampling system design, including the state machine design, dual-port ram usage, frequency design