搜索资源列表
BlockRAM
- xilinx BlockRAM 级联,利用Xilinx原语(非IP Core),更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
DoubleDort_RAM
- 双口RAM控制时序仿真 双口RAM控制时序仿真 -Control of dual-port RAM dual-port RAM timing simulation control timing simulation to control dual-port RAM Timing Simulation
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
ram_old
- 用来测试cpu的ram代码 其中包括几十条指令 cpu的vhdl也在本站有下-Cpu the ram used to test the code, including dozens of VHDL cpu instructions also have a website under the
RAMtestbench
- 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
ramvhdllib_06
- The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
rom
- 根据实验要求,对rom和ram进行验证,实现各项功能。-According to the experimental requirements of rom and ram for authentication, the realization of various functions.
wave_produce_VHDL
- --文件名:mine4.vhd。 --功能:实现4种常见波形正弦、三角、锯齿、方波(A、B)的频率、幅度可控输出(方波 --A的占空比也是可控的),可以存储任意波形特征数据并能重现该波形,还可完成 --各种波形的线形叠加输出。 --说明: SSS(前三位)和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号(ss)完成的(AMP的调节范围是0~5V,调节
FIFO
- FIFO中文应用笔记,对学习单片机RAM、大量数据处理很有帮助。-FIFO notes
profiles
- source code of counter,ram,lfsr etc
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷(GRAY)变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点,使得整个系统可靠性高和抗干扰能力强,系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构,使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
sj_work
- RAM控制的VHDL实现 真的很有用 -VHDL implementation of the RAM control true true useful useful
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
control
- Turbo码编码器时序控制模块,能够对于RAM,ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
ZBTSRAM
- 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
stackfiles
- VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower la
dpram2
- vhdl写的双口ram,真正实现双口通信-I write vhdl dual ram, true dual-port communication
lpm_ram
- 一个基于quartus的LPM_RAM例子,VHDL语言写的,通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
SouceCode_0f_DDR_SDRAM_Controller_by_VHDL
- VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.