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TESTRAM
- FPGA,双口RAM测试程序,仿真双口RAM工作时序,对时序的理解!适合对双口RAM不太了解的初学者使用!QUARTUSII8.0软件平台仿真通过!-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much
fifo_design
- 异步fifo的设计,能够很好的的完成,数据的缓冲,内部有ram存储器-The design of asynchronous fifo, Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
ram
- 代码实现了一个由32位寄存器组成的寄存器组,并有多个控制输入和两个输出,方便使用。-The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.
components
- quartus的几个IP核(PWM,RAM,I2C)-quartus several IP core (PWM, RAM, I2C)
DW8051
- 8051Ip核内部ram。很多8051iP核都没有内部ram,上传一个希望对大家有用-internel ram of 8051Ip
RAM.ZIP
- VHDL CODE FOR RAM AND ROM
BS
- 用EDA设计ROM和RAM及其应用,用VHDL语言编程实现字符、汉字的存取并用点阵显示-ROM and RAM design with the EDA and its applications, using VHDL programming language characters, Chinese characters, access to and use dot-matrix display
jj
- 本题设计一个数字存储示波器,以Xilinx公司20万门FPGA芯片为核心,辅以必要的外围电路(包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块),利用VHDL语言编程,实现了任意波形的单次触发、连续触发和存储回放功能,并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时,将外部输入信号经信号调理模块调节到A/D电路输入范围,经A/D转换后送入FPGA内部的双口RAM进行高速缓存,并将结果通过D/A转换送给通用示波器进行显示,完成了对中、低频信号的实时采样和高频信号的等效采
FIFO
- 设计了一个具有双时钟信号,双复位信号的FIFO,用于FPGA中的数据缓冲,RAM的定义是参数型,可以根据自己的需求,修改此参数,完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
CPU
- 包含CPU每部分器件的编写,通过改写RAM内容,可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
RamFifoVHDL
- Ram Fifo Core VHDL file
ram
- 用VHDL描述了RAM的读写,很好的一个小东东,要你好好学习,用于开发RAM-OK,OK,VHDL ,FPGA,RAM,WRITE AND READ ,YOU WILL LIKE IT,ARE YOU?
BoXingFaSheng
- 多功能波形发生器VHDL程序与仿真 功能:实现4种常见波形正弦、三角、锯齿、方波(A、B)的频率、幅度可控输出(方波 --A的占空比也是可控的),可以存储任意波形特征数据并能重现该波形,还可完成 --各种波形的线形叠加输出。 --说明: SSS(前三位)和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号(ss)完成的(AMP的调节范围是0~5V,调节量
ram
- vhdl program for random access memory and sequence detector
Ram-block-code
- It is a VHDL code for Block RAM
RAM
- ram code in VHDL with its test code
ram
- hi this is ram code in vhdl
6soft_247MHz_channel
- lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟
vhdl
- single-port RAM in write-first mode. module raminfr (clk, we, en, addr, di, do) input clk input we input en input [4:0] addr input [3:0] di output [3:0] do reg [3:0] RAM [31:0] reg [4:0] read_addr always @(po