搜索资源列表
verilog_prj_seq
- 序列检测器，检测序列“11010”，verilog HDL代码。-Sequence detector, detection sequence "11010", verilog HDL code.
alu_sequence_detector_1101
- It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
fsm_seq0101
- verilog状态机实现的序列检测器，本人仿真通过，绝对可用，欢迎大家下载学习。-verilog state machine sequence detector simulation by himself, absolutely free, welcome to download the study.
SCHK
- 10位序列检测器，有序列产生，分频器，按键消抖，序列检测，数码管扫描等几个模块构成，设计天津工业大学课程设计-10 sequence detector with sequence generation, dividers, key debounce, sequence detection, digital scanning, and several other modules, curriculum design, Tianjin Polytechnic University
prog_seq_FIN
- Verilog Programmable Sequence Detector on Spartan3E
Fsm
- 基于verilog的FSM设计，设计“101001”的序列检测器；包括testbench文件-The FSM based verilog design, design " 101001" sequence detector including testbench files
basic_1
- vhdl 语言实现序列检测器 -vhdl language sequence detector vhdl language sequence detector
XU-LIE-JIAN-CE-QI
- 用状态机实现序列检测器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
10010_xu_lie_jian_ce_qi
- 基于FPGA的序列检测器，能检测10010序列-FPGA-based sequence detector can detect a sequence 10010
bitdetect
- verilog代码编写110100序列的序列检测器，用状态机实现，包括仿真测试代码-verilog coding sequence detector 110100 sequence state machine implementation, including simulation test code
XULIEQI
- 用状态机实现序列检测器的设计 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出a，否则输出b- With a state machine sequence detector design Sequ
alu_sequence_detector_1101
- It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
partii_fsm_SequenceUsingCase
- verilog hdl code fsm sequence detector using case ,, an FSM that recognizes two specific sequences of applied input symbols, namely four consecutive 1s or four consecutive 0s. There is an input w and an output z. Whenever w = 1 or w = 0 for fou
src
- SEQUENCE DETECTOR IN VERILOG
checkfor1101
- 1101序列检测器，VHDL编写，外部输入任意序列，一旦检测到1101就亮led提示。-1101 sequence detector, VHDL prepared, external input arbitrary sequence, once detected 1101 bright LED tips.
jc1101
- 用状态机实现序列检测器的设计，了解有限状态机的设计与应用。-With a state machine sequence detector design, understand the design and application of finite state machines.
xuliejianceqi
- 序列检测器00101，包括源代码，testbench，ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
VHDL
- 先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
FSM
- 序列检测器，采用有限状态机实现，检测特定序列“101011”- Sequence detector, finite state machine, detection of a specific sequence 101011