搜索资源列表
jietiao
- 提供一个matlab程序，功能是将被Delta-Sigma调制器调制过的信号解调出来。-Provide a matlab procedures, functions will be Delta-Sigma modulator modulated signal demodulated.
one
- 上传一个将正弦函数通过Delta-Sigma调节器转换成正负一的脉冲信号。并分别激励同一系统，得到良好的一致输出-Upload a sinusoidal function by Delta-Sigma modulator converts a signal of positive and negative pulse. And separately driven in the same system, to obtain a good coincidence output
ak5386
- ALSA SoC driver for Asahi Kasei AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC.
Delta_sigma_PA
- A simulation of delta sigma modulator for digital power amplifier applications.
delsig
- matlab code for Delta Sigma Toolbox
data-integrity
- Asahi Kasei AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC.
hermes_rid
- AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC.
LTC2440_1
- 一款具有 5ppm INL 和 5μV 偏移的高速 24 位无延迟增量累加 (No Latency ΔΣTM) ADC LTC2440的源代码-A 5ppm INL and 5 V high speed 24 bit offset without delay increment accumulation (No Latency TM ADC LTC2440 delta sigma) source code
Accelerometer_AIs_RT
- cRIO FPGA example with FIFOs. Demonstration of fast data streaming through fifo. The FPGA Templates section has one template for Delta Sigma based modules and one template for SAR based modules. Under the FPGA target you will also find the DMA Channe
eachpart
- Simulink delta sigma modulator- each stage output
firstorder
- delta sigma modulator-first order
ADS1299
- TI公司的ADS1299是8路低噪音同时取样的24位delta-sigma ADC,并内置了可编程增益放大器(PGA),基准电压和振荡器,集成了脑电图(EEG)所需的通用特性.器件具有非常低的输入参考噪音:1.0 μVPP (70-Hz BW),没路的功耗5mW,输入偏置电流300pA,数据速率250SPS到16kSPS,C1.0 μVPP (70-Hz BW),CMMR为-110dB,可编程增益为1, 2, 4, 6, 8, 12或24,单极或双极电源工作,主要用在医疗仪器如EEG和ECG,听
DeltaSigma Converter with Analog Comparator
- Delta-Sigma converter with comparator and RRC circuit
ADS1252
- The ADS1252 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from a single +5V supply. The delta-sigma architecture is used for wide dynamic range and to ensure 24 bits of no missi
VERILOG
- 基础的几个verilog代码实现，讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)