搜索资源列表
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
Text-IO
- 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
inputoutput_textio
- 关于VHDL读取文件的testbench编写的ppt介绍，挺有用的-testbench for text_io,it is very useful,isn t it.testbench for text_io,it is very useful,isn t it.
test
- 从文件中读取波形文件的testbench例子，大家可以参考-Read from the file testbench waveform file example, we can refer to
VHDL
- 介绍Verilog HDL, 内容包括：Verilog应用，Verilog语言的构成元素，结构级描述及仿真 ，行为级描述及仿真，延时的特点及说明 介绍Verilog testbench，激励和控制和描述 结果的产生及验证，任务task及函数function 用户定义的基本单元(primitive)，可综合的Verilog描述风格等-Introduction Verilog HDL, including: Verilog applications, Verilog language
Testbench(Verilog)
- verilog验证平台的使用 很不错 很详细 想具体-verilog verification platform is more like using a very good specific
Spartan3E-LCD
- 一个基于Spartan3E板子的LCD接受的代码附带testbench-A board of LCD-based Spartan3E accepted code with testbench
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
TestBench
- TestBench for stop_watch in VHDL
VHDL
- 分别采用行为描述，数据流描述和结构描述 编写的VHDL代码 同时，含有各自的testbench-Behavioral descr iptions were used, the data flow schema descr iption and VHDL code written at the same time, with their testbench
DualPortRam
- VHDL Dpram including clock divider, D4to7, Scan4Digit and of course TOP level as well as testbench info
VHDLTESTBENCH
- 本文档对编写vhdl的testbench具有很大的参考价值，偶那个多方面考虑的-The preparation of this document, the testbench vhdl of great reference value, even considering that many
rsa.tar
- good working RSA code with testbench
FIR_CODE
- 4-taps FIR VHDL code with testbench
mppt_mod
- maximum power point tracking system (MPPT) VHDL code with testbench
high-efficiency-testbench
- 用VHDL编写高效率testbench 中文-Efficient testbench written in VHDL Chinese
4-bit-comparator-with-testbench
- Create a VHDL representation for a logical circuit of a 4-bit comparator. This comparator will have equal (=), smaller than (<) and larger than (>) output signals.
testbench
- VHDL和verilog的TESTBENCH 编写方法。非常好的资料。英文的,但很简单。-Written in VHDL-TESTBENCH. Very good information. In English, but very simple.
testbench
- FPGA逻辑实验中，用VHDL语言实现IP核生成的实验。-FPGA logic experiment, with VHDL language implementation IP nuclear generated experiment.
vhdl
- IIC源码VHDL文件。包括IIC master端的控制器实现及仿真文件。-IIC of VHDL source。Including IIC master controller implement and testbench.