搜索资源列表
9.4_PULSE_FRE
- 基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示 9.4.1 脉冲频率的测量原理 9.4.2 频率计的工作原理 9.4.3 频率测量模块的设计与实现 9.4.4 while循环语句的使用方法 9.4.5 门控信号发生模块的设计与实现 9.4.6 频率计的Verilog-HDL描述 9.4.7 频率计的硬件实现 -based on Verilog-HDL hardware Circuit of
fcout
- 频率计源代码,性能很好,verilog写的,顶层原理图,底层语言写的,效果很好,开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus
Freq
- 简易数字频率计,用Verilog HDL编写的,基于Quartus II实现,结构清晰,功能较为全面,能满足简单的频率测量要求
equal_precision_cymometer
- 采用等精度测频原理的频率计的程序与仿真,用verilog语言实现,可以仿真综合得到所想时序!
VerilogHDL_counter
- 采用Verilog HDL语言编写的数字频率计,被测波形分别为方波、三角波和正弦波;采用6个数码管显示结果,三档量程可调,工程价值很高,
onehehe
- verilog设计的4位频率计,可以测量方波、三角波、正弦波;测量范围10Hz~10MHz,测量分辨率1Hz,测量误差1 Hz;测量通道灵敏度50mv
CPU
- verilog编写CPU: 1. 哈佛存储器结构,大端格式; 2. 类MIPS精简指令集,支持子程序调用和软中断; 3. 实现了乘除法; 4. 五级流水线,工作频率可达80MHz(每个时钟周期一条指令,不计流水线冲突)。 -MIPS like CPU using verilog
dispdecoder
- verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
8-bitdecimalfrequency
- 学verilog时写的8位十进制频率计,开发环境为quartus II6.0.-When learning to write Verilog 8-bit decimal frequency, the development environment for quartus II6.0.
test1
- 4位数字频率计的verilog HDL设计,精度比较准的-4-digit Cymometer verilog HDL design, the accuracy of the quasi-comparison
eight_decimal
- 用VERILOG写的8位十进制频率计 注释非常清晰 有助菜鸟学习-VERILOG written with eight decimal Notes Cymometer help rookie learning very clear
LowFreCounter
- 实现对低频信号进行等精度测量的频率计verilog hdl代码-Realization of low-frequency signals, such as precision measurement of the frequency code verilog hdl
EDA_project
- 基于Verilog和VHDL的DDS程序 基于VHDL的8位十进制频率计 -Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer
pinlvji
- 数字频率计的Verilog HDL语言实现,已经通过仿真-Digital frequency meter Verilog HDL language implementation has been through simulation
freq_counter(Verilog)
- 数字频率计FPGA代码,用verilog语言实现。-Digital frequency meter FPGA code with verilog language.
Verilog-shuzipinlvji
- 数字频率计,基于Verilog HDL,内含哥哥功能模块子程序-Digital frequency meter, based on Verilog HDL, function modules containing subroutines brother
Verilog_HDL
- verilog 频率计 有分析过程和代码.-The verilog cymometer analysis and code
Verilog
- 自动售货机,乐曲演奏电路,4 位数字频率计等详细程序代码-Detailed code of vending machines, the music playing circuit, four digital frequency meter
frequency---base-on-verilog
- 基于verilog的数字频率计设计(源码)-frequency design base on verilog
frequency
- 基于Verilog HDL数字频率计的设计与实现(Design of Verilog HDL Digital Frequency Meter)