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zs
- 基于fpga的数字频率计,verilog编写,可修改闸门宽度0.1s/1s/10s,可测频率1hz~1mhz,包含整个工程,内部分频模块为了仿真方便改小了,后面注释为50mhz晶振下的分频值,可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire
pinlvji
- verilog 简易频率计的设置,包括整个工程-verilog simple frequency meter settings, including the entire project
daima
- 这是一个频率计的verilog源码 实现频率计数-this is a verilog program,it content a example impliment a frequnt counter.
quartus_works_second
- 基于verilog语言的,FPGA程序,实现频率计与数码管显示功能,转换频率48M,精度1Hz,量程1Hz~9999Hz,有欠频率和超频率提示,精度与量程可随外部设备改变而改变,在EP1C3T100C8上亲测通过-Based verilog language, FPGA procedures to achieve frequency meter with digital display, switching frequency 48M, precision 1Hz, range 1Hz ~ 99
FPGA_cymometer
- FPGA程序,verilog HDL语言编写,提供了一种频率计的实现方式,开发环境为Quartus ii 13.0,初学verilog HDL语言的同学可以参考下-FPGA procedures, verilog HDL language, provides a way to achieve a frequency meter, development environment for Quartus ii 13.0, beginner verilog HDL language students
frequency
- verilog编写的双量程频率计及仿真测试程序,采用500MHz系统时钟-verilog prepared dual-range frequency meter and simulation test program, using 500MHz system clock
freq
- 基于FPGA的频率计,用verilog语言实现,在标准时钟周期内进行计数,得到信号的频率。-FPGA-based frequency meter, using verilog language, the standard clock counted to obtain the frequency of the signal.
pinlvji
- 一个用verilog编写的数字频率计,利用FPGA实现计数功能,其中使用的测周法。-A written with verilog digital frequency meter, use FPGA implementation counting function, wherein the measured circumference method to use.
Frequency
- 实现频率计基于verilog语言,基于basys2板子。数码管显示。外部输入信号。-frequency countting based on verilog
frequency-meter---DEII
- verilog写的频率计 ,在数码管上显示10进制输入数字信号的频率。已在DEII上验证- verilog write frequency counter, decimal display frequency of the input digital signal in the digital tube. Verified on DEII
frequency
- 用verilog实现频率计设计,包括详细源代码-Using verilog to achieve frequency meter design, including detailed source code
freq
- verilog 编写的频率计 管脚绑定支持Xilinx Spartan6-verilog prepared frequency meter pin binding support Xilinx Spartan6
verilog_c
- 采用Verilong编写的等精度频率计,调试成功可测频率、周期、占空比、正负脉宽。-Written using Verilog and other precision frequency meter, debugging success can be measured frequency, period, duty cycle, positive and negative pulse widths.
sp6ex14
- verilog,ISE工程。倒车雷达实例,每100ms产生1个超声波测距模块所需的10us高脉冲激励,并用数码管以16进制数据显示经过滤波处理的回响信号的高脉冲计数值(以10us为单位),与此同时,蜂鸣器根据障碍物远近,也会相应的发出不同频率的响声。-verilog, ISE project. Reversing radar instance, every 100ms high pulse generating 10us required an ultrasonic ranging module
pinlvji2
- verilog语言,quartus下实现频率计,内附原理图以及详细说明。 一共6个.v模块,其中一个是top,其余都是子模块。 测量频率的原理很简单,对一定时间内待测信号的上升沿的个数进行记录即可。 单位khz,四位数码管,小数点可以处于其中任何一位,假设数码管由高到低定义成HEX3,HEX2,HEX1,HEX0,那么当hex0的小数点点亮时,表示xxxx khz,hex1的点亮时,xxx.x khz,依次类推。 为保证精度,当时xxxx khz时,最小分辨率应该是1khz,所以
pinglvji
- Verilog HDL 实现频率计,数码管显示1~9999Hz 开发环境ISE14.7-Verilog HDL frequency meter, digital tube display 1~9999Hz Development environment ISE14.7
fdiv0_256_14
- 利用Verilog HDL制作一个数控频率计,0~256可控(Use Verilog HDL to make a CNC frequency meter, 0~256 controllable)
8bit-freqDetect
- 题目1:设计一个8位数字显示的简易频率计。要求: ①能够测试10Hz~10MHz方波信号; ②电路输入的基准时钟为1Hz,要求测量值以8421BCD码形式输出; ③系统有复位键; ④采用分层次分模块的方法,用Verilog HDL进行设计。 ⑤写出测试仿真程序(Topic 1: Design a simple frequency meter with 8 digits display. Requirement: It can test 10 Hz ~ 10 MHz square wave si