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v16bbit_boothe
- verilog程序源码,实现两个16bit数乘法,使用booth算法,一种基于状态机实现,分层层次为datapath与controller两个子模块,testBench测试通过 -verilog program source code, and two 16bit multiplication using booth algorithm, based on the state machine implementation, the hierarchical level for the da
dianji
- 用VERILOG HDL编写的通过状态机控制步进电机的例程,很经典-VERILOG HDL prepared by the state machine to control the stepper motor routines, classic
paomadeng2
- 简单的跑马灯verilog程序,笔者是初学者,利用简单状态机编写的-Simple Marquee verilog program, the author is a beginner, use a simple state machine to write
AD9854verilog
- verilog 编写的AD9854配置代码 通过状态机转换来配置AD9854-CONGIURE the ad9854 dds
FSM
- 典型实例用FPGA来实现有限 状态机 FSM的程序编写-fpga fsm verilog
ddr_verilog
- DDR控制器的VERILOG代码;状态机;读写;刷新等操作-ddr controller,verilog
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
Traffic
- 交通灯控制器的Verilog代码,采用了三段式的状态机描述,适合学习和练习,包括了验证代码-A Verilog code of Traffic light controller, using a three-stage state machine descr iption suitable for learning and practice, including the verification code
a-simple-state-machine
- 简易状态机 verilog实现的简单状态机,全工程不错的 典型历程 值得学习入门很好的实验例程-Simple state machine verilog achieve a simple state machine, the typical course of the whole works good deserves learning entry good experimental routines
verilog_iic_at24c04
- verilog语言实现的iic协议通信,一段式状态机实现,结合按键和数码管,用来控制和显示数据-Verilog language the iic protocol communication, for some state machine implementation, buttons and digital tube, used to control and display data.
UART_RS232(verilog)
- /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit(即无奇偶校验位)的串口控制器,10个bit是1位起始位,8个数据位,1个结束位。串口的波特律由程序中定义的div_par参数决定,更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145,对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是:串口处于全双工工作
key
- verilog的按键消抖程序,利用状态机完成的-verilog the the key debounce program, the completion of the state machine
EMAC6
- verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well a
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块,代码通过状态机实现,开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
doorlock.rar
- 门锁 状态机 verilog 适用于digilent NEXYS2开发板,doorlock state machine verilog applied to digilent NEXYS2 board
cache
- 基于MIPS思维方式,verilog语言,简单的cache 控制器设计,状态机共分4个状态,同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
state-machine
- Verilog HDL编写的简单状态机程序。-The Verilog HDL written a simple state machine program.
lcd
- 这是一个用verilog写的LED的控制代码,其中主要是利用状态机的形式实现的-This is a verilog the write LED control code, which is realized in the form of state machine
ps_transfer
- verilog HDL语言编写的8位并串转换,使用状态机实现可综合-Using verilog HDL language realize parallel-to-serial conversion, using the state machine to achieve ,can comprehense
uart_state
- 基于状态机编写的串口通信实验,编程语言是Verilog HDL,可发送八位数据,在Altera的EP4CE15F17C8芯片上验证成功。(与另一个发送256位不同的是这个代码比较突出状态机的使用)。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif