搜索资源列表
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
seqdet
- Verilog编写的有限状态机的程序，实现对一二进制序列的检测，该有限状态机提供8个状态的，可以任意修改，作为测试。-Verilog written procedures for finite state machines to achieve the detection of a binary sequence, the finite state machine with 8 states, and can be freely modified, as a test.
EfficientSynthesizableFiniteStateMachineDesignusin
- 高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog
StateMachine-based
- FPGA上的利用状态机实现的分频的verilog程序-verilog source code StateMachine-based for FPGA
div_res
- 这是一个用VERILOG实现的除法的指令，用状态机实现的，希望对大家有用-THIS IS A CODE FOR DIV OF VERILOG。ITS USEFUL...
verilog_instance
- 20多个十分实用的verilog例子，如状态机，除法器等-More than 20 very practical verilog examples, such as state machines, divider, etc.
serial_in
- verilog 串并转换程序 状态机 有4位前导码 共转换3位 可自己修改后转换更多的串行数据位-Verilog serial signal to parallel signal transfer
FSM
- 这是用verilog硬件描述语言编的moore状态机代码-It is compiled verilog hardware descr iption language moore state machine code
example
- 我FPGA开发板的程序！！！包括数、码管iic、VGA、乘法器、串口。加法器、比较器、状态机等等等了，主要是VHDL的也有部分好似Verilog的。参考下吧-verilog...vga..uart...add...etc..
zuyuan
- 这是一个实现有限状态机的verilog编程的程序-This is a realization of finite state machine programming procedures verilog
zhuangtaiji
- 检测姓名序列的状态机。使用VERILOG编写。平台是QuartusII9.1。Cyclone -Detection of sequence state machine name. Prepared using VERILOG. Platform is QuartusII9.1. Cyclone III
lsh
- 基于Verilog的状态机的流程图及源代码-Verilog state machine based on the flow chart and code
statemachine
- 状态机可以实现几个状态之间的转换,这时使用qt编写的verilog文件-statemachine for inter change between any one of them
iiscode
- 用Verilog写的一个简单的IIs控制器，分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。 另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and syn
1602LCD
- 该程序是1602的verilog程序，该程序采用状态机编写-The program is 1602' s verilog program, the program prepared by the state machine
ywjc
- 采用状态机的方法实现移位寄存器，用Verilog HDL编写，已经通过验证。-The method uses the state machine implementation shift register, with write Verilog HDL has been verified.
xinjiaotong
- 自己编写的，使用Verilog语言辨析的在FPGA上实现的交通灯的红绿黄灯，用状态机实现，共有六种状态，红-绿、红-黄、左转弯、绿-红、黄-红、左转弯，每种状态配以数码管显示区分。-I have written, use the Verilog language Discrimination implemented in the FPGA, red, green and yellow traffic lights, a total of six states, red- green, red-
zidongshouhuojisheji
- 本文采用Verilog HDL描述语言实现自动售货机系统的销售动作，用有限状态机进行系统状态描述，自动售货机通电复位时，自动进入系统初始状态，本文设计的自动售货机控制系统主要可以实现投币处理、计算投币总额、输出商品，输出找零、余额计算并显示等功能。-This verilog hdl describe language used for automatic machines system of action, with a limited system of state, state, the v
zhuangtaiji
- 状态机的使用 verilog】 真的就这么多了-verilog