搜索资源列表
UART-master
- FPGA Based UART in Verilog
Verilog_uart
- 锆石科技 用Verilog实现uart通信，文件包括模块和顶层文件，直接解压缩在quartus上编译即可。(Zircon technology Verilog with uart communication, the file includes the module and the top file, the direct decompression can be compiled on the quartus.)
UART1
- 基于Verilog的串口RS232控制器(RS232 controller of serial port based on Verilog)
uart-master
- verilog语言实现URAT串口通信，便捷开发(Implementation of various basic circuits in digital circuits with Verilog language)
uart
- 一个具有固定波特率的 UART 串口收发器，可以实现 串口收发器，可以实现 9600 波特率的串口通信， 能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication, and can communicate with PC
eetop.cn_uart 源码 (Verilog)
- Verilog编写的UART通信模块，比较清晰(UART model wrote by Verilog)
VERILOG_UART
- Simple implementation of UART on Verilog
UART
- Verilog写的UART 协议。可用于FPGA RS232接口实现。(The UART protocol written by Verilog. It can be used for the implementation of the FPGA RS232 interface.)
uart_test_Verilog
- 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configura
Receiver_spartn6_v1
- Implement design of UART receiver in verilog
uart
- uart串口FPGA实现示例 example(uart serial interface example)
uart
- 用verilog实现UART串口收发。状态机形式实现，波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)
UART发送接收奇偶校验
- 状态机，串口收发，以及奇偶校验。 even_parity.v奇偶校验； receive_byte.v字节接收； send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)
verilog
- lcd1602 12864显示程序代码，串口传输数据代码(lcd1602 12864 code,UART code.)
apb-uart
- apb—uart模块，实现中断处理和异步收发数据并处理(APB - UART module, interrupting processing and asynchronous receiving and receiving data and processing)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
12345 keyuart
- verilog实现uart串口编程 FPGA板与PC传输数据(verilog uart processing FPGA and PC communication)
UART_FPGA
- FPGA下的UART串口通信协议及控制器设计(UART serial communication protocol and controller design under FPGA)
PC2FPGA_UART_Test
- 基于 fpga 的 uart 设计 波特率 115200(UART design based on FPGA)
VerilogUart_Modelsim
- 使用Verilog编写的UART ，用Modelsim仿真工程。(use Verilog Write UART Program, Modelsim simmulate the project)