搜索资源列表
Fix-data-send-UART
- Fix data UART send and receive verilog codes.
basic-cache
- Verilog codes for cache memory with direct mapping and write back policy.
proc_pipe
- A 5 stage pipeline CPU written in verilog codes
try_ram
- Verilog Codes for RAM-Testing. Write data in the RAM and read it out from the RAM. Tested on NEXYS 3.
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
RTL_Compiler_synthesis.pdf
- HOW TO SYNTHESIZE VERILOG CODE USING RTL COMPILER This tutorial explains how to synthesize a verilog code using RTL Compiler. In order to do so, let’s consider the verilog codes below.
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
lcd-with-spartan-3an-fpga
- This rar file contains the instruction and verilog codes for interfacing spartan3AN with LCD display.
boolean_function
- verilog codes for boolean function
RAM_basic
- RAM Implementation using Verilog Codes
fpga3_123
- Verilog Codes to understand verilog system tasks
antenna-effect
- 硬件电路设计中消除天线效应的电路RTL级Verilog代码-RTL grade of Verilog codes for reducing antenna effect
no
- My verilog codes.l vdkvmomvemcmemekmkem
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
rc4_crypt
- 自己写的rc4加解密算法部分的verilog代码，可综合，供大家参考-Write your own encryption algorithm verilog codes rc4 section can be integrated, for your reference
Verilog-Codes
- Bit serial Multiplier
gds8k_32bit_1M
- 一款SRAM的verilog代码及版图信息-verilog codes and layout information of a RAM
32-bit-carry-look-ahead-adder
- This file contains Verilog codes
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and