搜索资源列表
A-VHDL-Primer---Bhasker
- VHDL exaples project from CPLD or FPGA
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
40716003-VHDL
- What is VHDL? • VHDL stands for VHSIC Hardware Descr iption Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
carry-ripple
- carry ripple adder code (whole project) in vhdl using xilinx tool. VHD file has source code
VHDL-example
- VHDL的几个实用例程，能帮助开发工程的同学更好的完成项目。-Several practical VHDL routines to help students develop a better project to complete the project.
zkrMtr
- 1 button counter vhdl project
XSA-P2MOUSE
- simple ps2 mouse vhdl project
XSA-PS2KBD
- ps2 keyboard vhdl project
led-decoder
- 7 segment display decoder vhdl project
doc
- BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional
ControlWD
- 汽车尾灯控制器，用VHDL编写的。包括仿真。是一个完整工程-Car taillight controller, written by VHDL. Including simulation. Is a complete project
FPGAMP3_LUKA_Project_Proposal
- The goal of this project is to design a MPEG Layer III (MP3) player using a FPGA board. The FPGA will read MP3 source files, decode them into a 16-bit Pulse Code Modulated (PCM) output, and play the audio files through an external speaker.
uart_transceiver
- 一个通用串口通信FPGA程序。大家可以借鉴-a uart FPGA pragram.you can modify and use it in your project.
RS_232
- VHDL实现RS232串口通信，压缩包内有完整的quartus2工程，由顶层，波特率，发送，接收四个模块构成。外部电路只需要一片MAX232就能与串口助手或单片机通信。-VHDL implementation of RS232 serial communication, compressed within a complete quartus2 project from the top, baud rate, send, receive four modules. External circui
VHDL100
- VHDL的工程100道实例，内容比较好，适合初学者，上课老师的讲稿，通俗易懂！给大家分享下-Examples of VHDL project 100, the content is better for beginners, school speech teacher, easy to understand! To share with you
Project-Clock-plus-alarm
- 实现超多功能数字钟的vhdl硬件实现，可以实现校时校分闹铃，多模切换，多模同时工作-Ultra-versatile digital clock vhdl hardware implementation can be achieved when the school hours the school alarm, multi-mode switching, multi-mode simultaneously
de2_70_air_hockey_game
- Verilog/VHDL project that implements a Air-Hockey game using a DE2-70 board and a LTM touch panel.
uart-
- 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled