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New-Project.tar
- vhdl language program
project-2
- 4位偶数校验器，VHDL文件，检验偶数，内含有测试程序-4- bit even checker
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
project
- 睿行fpga开发板配套例程，verilog版本-ruixing fpga vhdl example
LCD-keyboar-rx-tx_gilang
- vhdl project keyboard asc-vhdl project keyboard ascii
vending-machine-project
- vending machine VHDL FPGA Altera
calculator-project-VHDL-FPGA
- Calculator PROJECT FPGA ALTERA DE-2
project-main-doc
- The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is
RAM2048X8
- you can add this code to your project if you need RAM2048X8
64point_FFT
- FFT64位，经过本人整理，工程已经编好，打开就可以马上用，适合新手看看(FFT64 bit, the project has been prepared, and can be opened immediately, suitable for novices to see)
variable_duty_cycle_pwm
- VHDL project in ISE Xilinx for PWM generation
7Seg. Display
- 7 Segments Display - VHDL Project
Cont 9 Display
- Counter up to 9 Display - VHDL Project
Cont 999
- 999 Counter - VHDL Project
TesteROM
- ROM Test - VHDL Project
DecHex7Seg
- Decoder Hex 7 Segments - VHDL Project
test56_PWM3
- VHDL 3 phase of PWM microsemi project
test59_TRIGU
- VHDL generating of trig signal microsemi project
test60_TRIGD
- VHDL generating of trig down signal microsemi project
test51_PLL
- VHDL How to use PLL-IP core microsemi project