搜索资源列表
RAM_module
- file contain vhdl code for RAM module
flashdemo
- quick test for Cypress RAm (here: 64 MB): VHDL example to test speed and quality of data: write and read process used.
Group27_lab5
- VHDL的基本门，ram，rom等的实现-VHDL basic door, ram, rom, etc. to achieve
randwofram
- read and write operations of ram in vhdl
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
ramchip
- vhdl code for ram design test bench
New-Folder
- vhdl code for sd ram.contents the vhdl documents
lab5
- m*n的ram，包含m*n个ram，使用VHDL编译，可在xilinx里面运行-m* n the ram, contains m* n a ram, using the VHDL compiler, which can be run in xilinx
sram
- 一款基于VHDL语言的静态RAM，RAM大小是128K-a kind of silence RAM
ram4bit
- ram 4 bit with cpld, xinix & language is vhdl.
VHDL_Sample
- VHDL VGA彩条发射器，里面有4个文件，分别是直接输出的，还有通过ROM查找颜色的，通过RAM和DRAM的-VHDL VGA color of the transmitter, there are 4 files, namely, direct output, as well as to find color by ROM, RAM and DRAM through the
ddr_sdr
- ddr ram控制器，使用vhdl语言实现-ddr ram controller,designed by vhdl
ram_wb
- 宽字符ram的实现，在quartus平台实现-wide word ram，desinged by vhdl on quartus platform
70T633_VHDL
- idt 双口RAN 70t633 VHDL驱动-idt DUAL RAM 70t633 VHDL driver
rom_decoder_ram
- 三八译码器 VHDL语言 ROM RAM-Thirty-eight decoder
ram_fpgavhdl
- fpga vhdl实现一个标准双端口ram，可以作为单端口或者双端口用 -fpga vhdl achieve a standard dual-port ram, can be used as a single port or dual port with a
alu_simulation
- VHDL alu unit design and simulation with RAM, ROM, clock generator and 2 simple programs to execute.
75_RAM
- RAM储存器 用VHDL编写,15位输入端口，8位输出端口，以及片选信号，使能信号，写信号-RAM using VHDL, with 15bits input ports, 8bits outputs and select signal, enable signal and writing signal.
circuit_vhdl
- this file is vhdl code for ram
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11