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performance
- 用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!-verilog prepared using the procedures used to calculate the error rate. the encoding and decoding process used in the!
pc104_fpga
- pc104接口的verilog代码，仅供参考-pc104 verilog interface code for reference purposes only
mt48lc2m32b2
- the verilog model of sdram-mt48lc2m32b2 device.-the verilog model of sdram - mt48lc2m32b2 d evice.
Plant
- 这些代码是用L-system语言，L-studio编译环境来实现相关功能的。主要是在实验室中的科研需要而编写的。 -these codes is L-system language, L-studio environment to compile the relevant functions. Mainly in laboratory research needs prepared.
dso_keyboard
- 本文件用于spi接口的键盘扫描模块，采用Verilog语言.-spi this document for the keyboard interface scanning module, using Verilog language.
uartvhdl
- 一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART
xapp616
- A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx-A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx
yimazhenque
- 47译码器器的verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-47 decoder for verilog source code, compiled simulation, absolute authenticity, helpful for beginners
lpm_mul
- ８＊８的乘法器verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-8 * 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
binary2bcd
- This build is for developing a \"binary-to-BCD\" converter for use in // displaying numerals in base-10 so that people can read and interpret the // numbers more readily than they could if the numbers were displayed in // binary or hexadecimal
fpga_coder_module
- 本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.-FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.
RSSI_contr
- VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage
lcd_controlveriloghdl
- 使用Ｖeriolog hdl 编写手机屏测试程序．-Veriolog hdl prepared to use cell phone screen test.
Verilog-HDL
- 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples w
i2c_master_top
- i2c主模块的底层驱动,使用方便简单,可以用任何才c开发工具开发-i2c main module of the bottom-driven, simple and easy to use, can be used before any c Tools Development
ddr_sdram_controller_vhdl
- ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
i2c_slave_model_verilog
- 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.
mt48lc8m16a2
- sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
easylight
- easydetect程序，是交通灯的verilog实现-easydetect process, the traffic lights to achieve verilog
trellis_verlog
- ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code