搜索资源列表
TestBench
- 通用控件测试床，内含进度条、树形控件、list控件等常见控件，可以为C++新手上路者练习控件使用提供快捷方便的框架。-common control test bed consisting of the progress of the tree controls, list control and other common controls for the C Started practice controls used to provide fast and convenient framewo
shift_register_testbench
- 16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
SOC-normal-testbench-and-verification-methology.zi
- 属于论文的形式，介绍比较详细，在万方数据库中载的，有参考价值-papers belonging to the form, a more detailed briefing, in the popular database contains the reference value
verilog_testbench_preliminary
- verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
i2c
- I2C controller的源码，包括TESTBENCH在内，里面包含有EEPROM的behaving model，前些日子在本站下了一个EEPROM的behaving model，发现可能只是作者的初版，里面错误比较多，因此上传一个能编译拿过来就能用的环境。
testbench
- 一个自己编写的全数字锁相环及其测试向量，比较简单但功能基本达到。
testbench
- 32位除法器的测试程序， 由随机向量产生函数产生一组随机数 来验证计算书否正确
ddstest
- 实现dds的testbench，很有帮助
testbench
- ddr sdram controller datd module source code
testbenchcpu8080
- this is code testbench cpu -this is code testbench cpu 8080
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
alu
- ALU modeling verilog codes and testbench
cpu86model
- This is intel 8088 x86 IP core, contain software complier & modelsim testbench
TESTBENCH
- 一个关于testbech写法的文档，很经典-A written document on the testbech very classic
testbench
- vhdl modelsim testbench examples-vhdl modelsim testbench for modelsim with vhdl examples
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
wave
- TESTBENCH OF CARDIO SYS-TESTBENCH
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
shift-register-and-testbench
- Shift register and testbench in verilog