搜索资源列表
MFSK-VHDl
- MFSK调制程序，里面有仿真结果，VHDL语言编写，语言简单，易学易用。-MFSK modulation process, there are simulation results, VHDL language, language is simple, easy to learn and use.
VGA
- 采用VHDL编写的VGA接口源程序和顶层原理图，程序经过调试和仿真，适合相关开发人员-VGA
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
serial
- 利用VHDL语言编写的串口程序，可以在Quartus2环境下编译下载-Use the serial language VHDL program can be compiled in an environment Quartus2 Download
de1_fsm
- 自动售货机的程序，全套，直接下载到板子就可以了！-VHDL for automatic！
vhdl
- 有一个关于VHDL的教程，可以学习一些VHDL的程序的写法-There is a tutorial on VHDL, VHDL can learn some of the wording of the procedure
RS232
- 关于RS232的VHDL程序，具体是什么还不是太清楚，不过程序还是可以借鉴-RS232 on the VHDL program, specifically what is not too clear, but the procedure can still learn from
proiect
- VHDL CODE FOR MULTY CYCLE
project3
- 用VHDL语言实现一个10秒倒计时电路，要求使用8*8点阵显示计时结果-VHDL language used to achieve a 10 seconds countdown circuits require the use of 8* 8 dot matrix display timing results
trace_matrix
- VHDL实现矩阵，可用于点阵板的输出、扫描电路。-use VHDL to build up trace_matrix
17jie_fir
- 采用VHDL语言实现17阶的数字低通滤波器的设计-VHDL language used to achieve 17 the number of bands of low-pass filter design
SupportDesignFiles
- use VHDL to design a game in FPGA
VGA
- VHDL Code For display a picture on Monitor
EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
test4
- vhdl数字设计实验,可以实现4x4小键盘的动态扫描-vhdl digital design experiments to achieve a dynamic 4x4 keypad scan
vhdlshili
- 多个vhdl 实例，USB UART I2C VGA-vhdl USB UART I2C VGA
clock
- 本文档采用VHDL语言编写了一个数字时钟的程序，该数字时钟采用24小时制计时，可以实现整点报时，时间设置，闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clo
d100
- des开源实现,vhdl文件格式. des 1-des design
prawn
- Prawn is a simple eight-bit microprocessor based on the sample processor described in Chapter 9 of "VHDL : Analysis and Modeling of Digital Systems"by Z. Navabi, McGraw-Hill,Inc. 1993. We have added some features such as interrupt, stack and some con
cpu
- 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL