搜索资源列表
top_clock
- 多功能数字钟，有校时，仿广播报时，整点报时，闹铃等功能！-Multifunction digital clock, there are schools, the fake radio timekeeping, the whole point timekeeping, alarm and other functions!
mt48lc4m32b2
- SDRAM module Verilog HDL-SDRAM module Verilog HDL
BISTProject
- BIST test doing project, in verilog.
i2c
- i2c master controller, free ip
music_disply
- 音乐播放器 中的数控分频器 后续还需要添加一个分频的电路-Music player in the follow-up of NC divider also need to add a sub-frequency circuit
Digital_Integrated_Circuits_by_Rabaey_2nd_edt._-_
- fpga using vhdl language
CycloneIII
- 有关FPGA的AS、JTAG配置的中文资料-The FPGA-AS, JTAG configuration of the Chinese data
I2C_SLAVE
- I2C slave端。可支持1带多。本人已经过调试，确认是可用的。-I2C slave side. Can support more than one band. I have been debugging, sure there is available.
APU
- 音频处理单元 vhdl 代码 很不容易找来的-Audio Processing Unit vhdl code
PS2LCDController
- PS2键盘LCD显示控制器的vhdl代码，很难得-PS2LCDController vhdl code
rsencoder_latest.tar
- reed solomon encoder (255,239) verilog source code
RANDOMIZATION
- DVB 数据随机化程序,标准接口,已应用~!-DVB data randomization procedures, standard interfaces, has been applied ~!
SYMBOL_MAPPING
- DVB QAM符号映射!已经应用于产品.标准TS流接口-DVB QAM symbol mapping! Has been applied to products. Standard TS stream interface
32Bitaludesign
- Design of simple 32 bit alu for SPARTAN 3 paltform
IO
- FILE INPUT OUTPUT USING VHDL SOURCE CODES
sha_core
- sha码生成电路，包括测试和仿真环境。 sha码生成电路，包括测试和仿真环境。-sha code generator， include test and simulation scr ipt。
frequency_generator
- DDS in our camera design
FPGA_SOPC_PWM
- 将此文件解压缩，会得到一个"ip"目录，将此目录放入你的项目中，就可以在sopc中import到一个叫pwm的组建了。解压缩还会得到一个C语言文件，它是与硬件配合的Nios2_C代码 -Extract this file will get an " ip" directory into this directory in your project, you can import into the sopc in the formation of a called pwm.
soft_vhd
- Soft decoder Viterbi on VHDL
ver1
- Decoder Viterbo on vhdl