搜索资源列表
FFT16
- 基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA
m序列
- Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
jtag_verilog
- verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
C_16450_edit
- 16450异步通讯接口，ALDEC提供，修正版（由网友zhy修改，修正一些错误-16450 asynchronous communications interface, providing ALDEC, the revised version (from netizens. Changes amendments to some errors
RD1006
- VHDL编程 : out std_logic -- Transmitter control DataBits : in std_logic_vector(1 downto 0) StopBits : in std_logic_vector(1 downto 0) ParityEnable: in std_logic ParityEven : in std_logic ParityStick : in std_logic TxBreak
control0
- systemverilog编写的cpu读写mem程序-SystemVerilog prepared by the cpu readers mem procedures
fifo0
- systemverilog编写的fifo例子-SystemVerilog examples prepared by the fifo
SVDrink
- Systemverilog 编写的贩卖机代码-Systemverilog preparation for the sale code
statemachine_mult
- veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
xapp195
- signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
20060215
- 叮叮-replaced behind the horn behind the horn behind the horn behind
Verilog_add4
- add4 verilog code -add4 Verilog code
dct_mac
- dct verilog code for image -Extra Verilog code for image
trafficontrol
- 使用verilog编写的交通灯控制程序，各方向通行时间可调，绿灯5s闪烁，在maxplus下调试通过，附仿真波形，在EP系列实验板上测试成功-use Verilog prepared by the traffic lights control procedures, the passage of time adjustable direction, green 5s flickered in maxplus under debugging, simulation waveforms with t
verilog_lcd
- 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
Altera_uart_VHDL
- FPGA/CPLD应用,uart通讯VHDL原码.-FPGA / CPLD applications, UART communications VHDL source.
Altera_uart_Verilog
- FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source
clock2001
- 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
crcDecode
- 比较完善的CRC编码VerilogHDL描述-more perfect descr iption of CRC coding VerilogHDL
PAOBIAO_V
- 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL descr iption