搜索资源列表
aes_encryption
- aes加密算法的VHDL代码实现，在FPGA芯片上调试过
Algorithms
- 密码算法AES,DES,IDEA,MD5等的基本理论和硬件加速方案，对算法进行fpga硬件加速的优点等
3DES_FPGA
- 介绍了3DES加密算法的原理并详尽描述了该算法的FPGA设计实现。采用了状态机和流水线技术，使得在面积和速度上达到最佳优化；添加了输入和输出接口的设计以增强该算法应用的灵活性。各模块均用硬件描述语言实现，最终下载到FPGA芯片Stratix EP1S25F780C5中。
crc
- 基于FPGA的crc设计，有一定的参考价值，写的比较详细
aes加密算法实现，经过FPGA验证的
- aes加密算法实现，经过FPGA验证的！,aes encryption algorithm, after FPGA validation!
des3.rar
- 3des加密算法实现，经过FPGA验证的！,3des encryption algorithm, after FPGA validation!
RIJNDAEL_DE_TOP
- AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
sha_core
- 安全散列函数的VERILOG实现，通过了fpga验证，在系统正可以直接当IP盒应用-Secure Hash Function VERILOG achieve, through the FPGA verification, the system is can be directly applied when the IP box
sha
- sha加密算法实现，经过FPGA验证的！-sha encryption algorithm, after FPGA validation!
FPGA
- 这是一个基于FPGA的加密/解密算法的简单介绍，并阐述了它的好处。-This is an FPGA-based encryption/decryption algorithm is a brief introduction and explained its benefits.
khalil2006_true_random_number_generator
- a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
sha
- 内带3个sha1的C源码。经验证都可用。在我们项目中，已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
AES-implementation-based-on-FPGA
- 一种基于FPGA的AES加解密算法设计与实现，对于对AES算法效率的研究有参考作用-FPGA-based AES encryption and decryption algorithm design and implementation of the AES algorithm for the efficiency of a reference
project-report
- documentation of Implementing a 1024-bit RSA on FPGA
AES-based-on-FPGA-jiami
- 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
Encryption-SATA-IP-Based-on-FPGA
- 本文首先分析了目前常用的硬盘数据加密方法，并在比较各种加密方案的基础上给出了基于FPGA的加解密SATA IP设计方案。本文介绍设计SATA IP相关的基础知识，包括SATA的体系结构。本sata IP已在Xilinx spartan-6系列上实现并产品化，具有低成本优势，且可以根据用户意愿更换加密算法和使用私有的加密算法。本文还论述了加密SATA IP的各种应用前景。-This paper firstly analyzes several common ways of Hard Disk da
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
AES-on-FPGA
- AES算法在FPGA上的实现，对AES算法所用的器件资源进行了总结-AES on FPGA the Fastest to the Smallest