搜索资源列表
Q24_MODEM
- 基于wavecom公司的Q24_plus GPRS/GSM 模块的无线modem的原理图设计，软件格式为ORCAD的DSN-On wavecom' s Q24_plus GPRS/GSM wireless modem module, the schematic design, software ORCAD format of the DSN
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
USB2.0
- UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。 -UTMI called USB2.0 Transceiver Macrocell Interfac
dataacquisitionwithFPGA
- 用fpga+usb显现的4通道800K的数据采集方案。-Fpga+ usb with emerging 4-channel data acquisition program of 800K.
viter2
- verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl
top
- rfid 电子标签设计数字基带处理顶层模块设计-rfid electronic card design diginal signal process of top module design
up_buhuo
- 这是一个VERILOG接收端捕获模块，扩频码32倍，可以检测到相关峰-This is a VERILOG receiver capture module ,the spreader is 32,it can test the correlation peak
sqrt
- it is a sqrt module ,with test bench.
8b10b_pdf
- 8b10b编解码设计的pdf文章,用于现代千兆网通信,快速串行通信.-.pdf paper
GPS
- 国外一个大学的详细软件接收机M文件,在MATLAB环境下可以运行-asoft-definedgpsreceiver
ca_code_gen
- CA_Code_Generator.vhd用于生成GPS的32颗卫星的CA码程序，经过测试验证并消除了毛刺；CA_TEST_BENCH.vhd内带测试程序，直接可调用MODELSIM进行测试验证，留有用户接口，方便用户产生其他卫星的CA码。-CA_Code_Generator.vhd used to generate the 32 GPS satellites CA code program, tested and verified to eliminate the burr CA_TEST_
usb20
- 通用接口usb2.0的verilog开发代码-Common interface usb2.0 development of the verilog code
Frame_Detection
- 802.11a帧检测源码，包括帧同步，书上光盘带的源码。-802.11a frame detection source, including frame synchronization, books, CD-ROM with source code.
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
ccf
- 实现SIN、COS的语言，基于CORDIC的应用-The realization of SIN, COS language, based on the application of CORDIC