搜索资源列表
multi
- 基于CPLD/FPGA的十六位乘法器的VHDL实现-Based on CPLD/FPGA multiplier of 16 to achieve the VHDL
Mul
- VHDL乘法器 四输入 四输出的代码设计-VHDL multiplier four input four-output code design
Multi11Mulply
- 本程序是11位带符号位的乘法器，其中最高位为符号位(sign)，中间7位是指数部分(Exponent)，最后3位是尾数(Matissa)。表示数据的范围是-2^-63-----+2^64.该工程文件有完整的程序，以及波形,验证正确。-This procedure is the unsigned 11-bit multiplier, one of the highest for the sign bit (sign), are between 7 part Index (Exponent), th
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
multi8x8
- VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier
Multiplier
- 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial
multiplier
- 乘法器在FPGA中的VHDL代码实现教程-Multipliers in the FPGA code in VHDL Tutorial
mul24x24
- 24位x24位的乘法器 十分详细24位x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位x24位的乘法器-24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica
Multiple
- 高效的乘法器设计，既节约面积，又提高性能，同时减少开发周期-Efficient multiplier design, both to save space and improve performance while reducing the development cycle
multiprocessor
- 简单的乘法器的内核测试，已经验证通过，VLOGER编写-The core of a simple multiplier tests have verified through, VLOGER prepared
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
16bit_mult
- 16位的无符号数乘法器，自己写的，经得起验证，注释很详细-16-bit unsigned multiplier, its own written
8bit_mult
- 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
matrix3x3
- 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
mul8b
- 有VerilogHDL编写的8位乘法器，可以综合。-Have been prepared in 8-bit multiplier VerilogHDL can be integrated.
BBooth
- 基verilog 布斯乘法器 4位位宽，本人不才，仅做参考-Booth multiplier based verilog
jiaotongdengsheji
- 乘法器 简单的乘法器编译 用VHDL自己编的-Compiled using a simple multiplier multiplier VHDL own series
6345252
- FPGA应用实例，FPGA片上硬件乘法器的使用，编程语言vhdl-Application FPGA, FPGA-chip hardware multiplier to use, programming language vhdl
multiplier_ip
- 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE