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adder3
- 此源代码是基于Verilog语言的七人投票表决器 、2 个 8 位数相乘 、8 位二进制数的乘法 、同一循环的不同实现方式、使用了`include 语句的 16 位加法器 、条件编译、加法计数器中的进程、任务、测试、函数、用函数和 case语句描述的编码器、阶乘运算函数、测试程序 、顺序执行、并行执行，特别是七人投票表决器，这是我目前发现的最优的用硬件描述的源代码。-The Verilog language source code is based on the seven-vote, and
modulo-2^n-2^k-1-adder
- 用Verilong语言编写的模2^n-2^k-1加法器，该加法器多用于基于余数系统的蒙哥马利模乘运算。 -Implementation of modulo 2^n-2^k-1 adder Using Verilog.This adder can be use for RNS Montgomery Multiplication
fir
- 利用系数奇对称的性，节约一半乘法器资源，实现平行FIR滤波器的功能。-The function of parallel FIR filter is realized by using oddly symmetric coefficients and saving half of the multiplier resources.
Multiplier
- 复用全加器来实现乘法器, 通过从右到左互为输入输出，实现低位计算。最左向高位输出。具体要求请参见附带的PDF。-Multiplexing a multiplier to achieve full adder, input and output by each other right to left, the least significant bits is calculated. Most left output to high. Specific requirements Refer to
dfe_filter
- DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
lesson1
- Quartus 乘法器搭建 ，数字电路实验例程，初学者可参考-Quartus multiplier build, digital circuit experimental routines
mux8
- 利用拨码开关，实现四位二进制与四位二进制的乘法器，结果转换为十进制，并通过数码管显示。-Using the DIP switch to achieve four binary and four binary multiplier, the results are converted to decimal, and through the digital display.
fec
- RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
booth
- 16位booth乘法器的实现：先将被乘数的最低位加设一虚拟位。开始虚拟位变为零并存放于被乘数中，由最低位与虚拟位开始，一次判定两位，会有4种判定结果。(The 16 bit booth multiplier to achieve: first the least significant bit is added with a virtual position. Start a virtual becomes zero and stored in the multiplicand, startin
e55_mul_addtree
- 实现4位乘法器的流水线操作计算，便于理解流水线(The implementation of pipelined operation of 4 bit multiplier is convenient for understanding pipelining)
verilog
- 里面包括乘法器等多个verilog编码整理，大多数的编码应该都在内(It includes multiple Verilog coding collation, such as multiplier, and most of the codes should be included)
Lab4
- 布斯(Booth)乘法器是一種透過編碼後再運算所得到較佳效能乘法器 請嘗試描述說明 1. 布斯乘法器原理 2. 布斯乘法器組成架構 3. 並嘗試完成布斯乘法器(The Booth multiplier is a better performance multiplier that is encoded and then computed Please try to describe the descr iption 1. Booth multiplier principle Boo
multi_booth
- booth乘法器,实现普通booth乘法算法(Booth multiplier to implement the common Booth multiplication algorithm)
FIR
- 采用加法树设计8位乘法器，具有流水线结构7阶FIR滤波器，输入序列信号字长4位表示，并且是无符号数。(An adder tree is used to design the 8 bit multiplier, which has a pipelined 7 order FIR filter. The input sequence signal is 4 bits, and it is an unsigned number.)
multiplier_8bit_top
- 两个8bit无符号整数相乘，模块分为控制模块和数据路径(Two 8bit data multiplies)
DIV
- 将两个32 有符号数相除，得到一个32 位商和余数，其中余数符号与被除数符号相同。(Two 32 Division has a number of symbols, get a 32 bit quotient and remainder, the remainder with the same divisor symbol symbol.)
MULT
- 将两个 32 有符号数相乘，得到 一个 64 位带符号数(By multiplying two 32 signed numbers, we get a 64 bit signed number.)
vhdl
- 用VHDL语言实现CD4527（BCD比例乘法器）仿真(The simulation of CD4527(BCD proportional multiplier))
wallace_multiplier
- 华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)
8点fft
- 用quartus软件、verilog语言编写的8点fft源代码，代码简单易懂，整个代码只用了一个乘法器和一个加法器