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alarm_ok_1
- 用ATmega16实现的多功能带音乐闹铃（老鼠爱大米）的数字时钟，有3个功能键设置。具体功能为：秒表计时，闹铃音乐，时钟，校时设置。可以学习状态机的编程思想。-ATmega16 achieve with the music with multi-function alarm (Lao Shu Ai Da Mi) digital clock, There are three function keys installed. Specific functions : stopwatch time,
VHDL_Development_Board_Sources
- 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development
trafficLight-verilog
- 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
0809conventorvhdl
- 1.AD0809转换器的vhdl实现 2.用状态机来实现不同状态的动态切换，思路明晰简单实现。 3.内含注释，易于修改和理解 4.对数码管的动态扫描,显示 -1.AD0809 converters to achieve the two vhdl. Using the state machine to achieve the different states of dynamic switching thinking, clarity simple to achieve. 3. N
key_state_mechine
- 4*4矩阵键盘扫描函数,用状态机实现,不用延时以消抖,只需在一个定时10~12ms左右的中断函数里调用,从而节省了单片机时间-4 * 4 matrix keyboard scan function, the state machine to achieve, not delay to eliminate buffeting, only in a regular 10-12ms about the interruption function within the call, thereby sav
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
state_machine
- 使用8位控制器picoblaze实现状态机的源代码-use eight picoblaze achieve controller state machine source code
VHDL-status
- VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
vgactrl
- vga控制电路原码。主要有时序产生模块，彩条产生模块和接口模块。改程序主要用状态机来实现，两个计数器来控制状态的翻转。-vga control circuit original code. Sequencers have a major modules of exotic produce modules and interface modules. Procedures in the main state machine to achieve, two counter to the state
st_11
- cpld状态及设计。 很好的文章。 要设计vhdl状态机的话，最好看看。-cpld state and design. Good paper. Vhdl to design the state machine, the best look.
VHDLexample49
- VHDL的49个例子，例子丰富，有计数器、状态机、寄存器、汉明纠错码编码器、游戏程序-VHDL 49 examples, examples of rich, counters, state machines, register, Hamming ECC encoder, Games, etc.
statekey
- 一个用过的最好的用状态机做的键盘程序，可代替任何键盘-used one of the best state machine with a keyboard, may replace any keyboard
irctl
- 状态机的典范-HT6222红外遥控芯片接收程序-state machine model-HT6222 infrared remote control receiver chip process
03034
- verilog中的一个不用状态机和决断函数就可以实现多重函数赋值的例子，希望对你用帮助。-verilog of a state machine and no decisive function could achieve multiple functions assigned to the case, you want to help.
13-310010_FSM
- 10010序列检测，用状态机来实现，非常方便-10010 Sequence Detection using the state machine to achieve very convenient
PN-arraycheck
- 在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器
maxbijiao
- 在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器
modem
- 一种MNODEM的控制程序.采用状态机的机制实现.
verilog_usbblaster
- 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机