搜索资源列表
divider
- 除法器，经过验证,性能优良，值得下载，应该是定点除法的-divider,it is verified and good performance
divider
- 用verilog实现一个被除数位8位、除数为4位的高效除法器-Verilog to achieve a dividend of 8, division by four efficient divider
chufa
- 用VHDL设计的四位除法器，可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
divider
- 基于移位相减运算的除法器设计，完整的设计工程文件在divider文件夹下-Based on the shift subtraction divider design, complete design project file divider file folder
VHDL_book2
- add4a：4位加法器的设计 add8a：8位加法器的设计 subtract：4位减法器的设计 addsub： 4位加法器/减法器的设计 shift4：移位寄存器的设计 mult4：乘法器设计 div8：除法器设计 alu4：算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
BCD_ALU
- bcd码的ALU单元，包含全加、全减、乘法、除法器-bcd code ALU unit, including All-Canadian, all subtraction, multiplication, division, unit
divider_with_cache
- 带缓存的除法器,包括test bench，在普通除法器上加上缓存功能-divider with cache
div_nonrestoring
- 用verilog 实现的除法器 ，被除数32位 除数为16位-Divider using verilog realize the dividend 32 divisor is 16
BCD_divid_new
- VHDL语言编写的8位BCD除法器，可以实现浮点数计算，只支持正数运算，并用isim进行仿真-VHDL language 8 BCD division, can achieve floating-point calculations, which only supports a positive number arithmetic, and use isim simulation
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器，除法器的设计-Achieved through verilog hdl adder multiplier, divider design
a
- 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写-verilog ise divider
lab4_5
- 用VHDL实现串行除法器，16位被除数，8位除数-Using VHDL serial divider, 16 dividend, divisor 8
divider
- 位数可以任意修改的除法器，本人亲自测试，可以使用，效率和使用资源都是很少的-its a very good divider based on Verilog HDL
divider_32bitdivby16bit
- verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.
chengfachufa
- ISE13.2的SPARTAN-3E 乘法除法器-ISE13.2 the SPARTAN-3E multiplication Divider
FPGA_Divider
- 本源码是用verilog语言编写的FPGA的除法器和74LS138及D触发器模块。-The source code is written in verilog FPGA divider and 74LS138 and D flip-flop modules.
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
chufaqi
- 用vhdl编写的N位除法器，适合初学者学习和编程- written in VHDL a N divider, suitable for beginners to learn and program
div
- 除法器设计，基于FPGA，实现除法运算，在实物上测试通过-Divider design, based on FPGA, to achieve the division on the physical test
chufa
- 开放式实验，CPU实验除法器，一个简单的除法器-Open experiment, CPU test divider, a simple divider