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vhdll
- 输入为8421BCD码，输出为8421BCD码。 程序中自动对输入进行转换，将8421BCD转换成余3码，然后采用修正函数实现加法，并且利用程序将加法结果转换成8421BCD码进行输出，且输出转换前后的中间结果。 -8421BCD code input and output for 8421BCD yards. Procedures for automatic input conversion, will be converted into 8421BCD I 3 yards, and
Quaalu
- ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲-ALU arithmetic logic unit to achieve a simple, using VHDL language, can be additive, subtractive, and the place and move around only one clock pulse
ex01_asm_ADD1-100
- 这是用asm编写的加法程序，是用16位的凌阳单片机汇编-This is asm2 procedures for the preparation of the additive, used 16 of Sunplus MCU Series
10fenpingqi
- 1、分别用IF语句和CASE语句设设计一个10分频器。 2、设计一个24进制加法计数器。 3、设计一个有使能端控制的4位减法计数器。 4、用case语句设计一个3-8译码电路 5、用CASE语句设计一个共阳极的七段译码电路。 6、已知输入信号为6MHZ，现需要输出2HZ信号，分别用if语句和CASE语句设计能实现该功能的电路 7、已知输入信号为9HZ，现需要输出2HZ信号，分别用if语句和CASE语句设计能实现该功能的电路 -1, respectively, with
fanyi
- The invention of the compound additive for alkaline PH value of more than 13 strong base will not only be able to prevent soil acidification, can effectively improve the soil acidic, as well as the rich soil of minerals, in the air to absorb the carb
calcCFARthreshold
- Compute Classical detection threshold for radar detection under additive Gaussian white noise criterion and specified false alarm probability. -Compute Classical detection threshold for radar detection under additive Gaussian white noise criterion
adder_2
- 这是一个加法器模块，实现用户所需要的加法功能-This is an adder module, the user needed to achieve additive function
P01_asm_MyFirst
- 凌阳单片机的第一个程序，汇编语言实现加法-Sunplus first single-chip process, assembly language to achieve additive
Yang2008_A_study_of_inverse_short-time_fourier_tra
- We propose a new vector formulation of STFT. We derive a family of inverse STFT estimators and a least squares one. We discuss their relationship and compare their performance with respect to both additive and multiplicative modifications to
CORDIC
- 用VHDL语言，利用迭代移位算法cordic实现告诉加法功能 -Using VHDL language, using iterative shift algorithm to achieve told additive function cordic
jishiqi
- 简单但是齐全的单片机计时，具有断电不丢失功能，接通电源继续累计时间，每天可单独计时，单独计时的人工累加，否则计满96小时自动累加-Simple but complete single chip timing, a feature not lost power, turn on the power continue to accrue time, daily time alone, time alone artificial additive, or automatically accumulat
C8051FO20
- C8051F020系列:电机测速 定时器二十进制转换 加法 18B20测温 步进电机 查表 串口通讯.-C8051F020 Series: motor speed timer 2 decimal conversion additive 18B20 temperature stepping motor look-up table serial communication.
noise
- 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
1_ADDER
- 实现加法功能,是半加法器，可扩充为全加法器。-Achieve additive function is half adder, full adder can be expanded to.
code
- 某数据传输系统，试图利用300-3400Hz的话音通 道进行载波传输，波形信道为加性高斯白噪声信道。 –采用线性传输，收发两端拟采用滚降系数0.5的根 号升余弦滤波，以解决采样点失真问题。 –以下仿真采用无记忆采样信道模型，其中受器件限 制，复基带采样点平均功率受限为1，复基带采样 点噪声功率为可调参量-A data transmission system, trying to use 300-3400Hz voice channel for carrier transmission, wave
AWGN_VerilogDesign-master
- 加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用-Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly