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CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
canbus
- 实现CAN总线的通信，并通过测试验证，用verilog在FPGA上实现-CAN bus communication, and tested to verify that, in the FPGA using verilog
CAN_IP.rar
- 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。,This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
canbus
- CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
canbus
- verilog 和VHDL实现的can总线接口代码-the realization of verilog and VHDL code of the can bus interface
verilog
- 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some o
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
can_latest.tar
- VHDL/VERILOG FOR CAN BUS Core
can
- can总线的verilog设计与实现，很好的资料哦-the implention of can bus with verilog
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
can-bus
- CAN总线控制器的VERILOG工程文件,很实用，工程是ISE可以打开，也可以只使用工程里面的代码-can bus project with VERILOG
verilog
- 都是介绍VHDL的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
the-verilog-code-of-can-usb-i2c
- CAN总线，I2C，USB等的FPGA实现源码-CAN bus, I2C, USB, etc. FPGA implementation source
verilog
- opencore can bus verilog design file-opencore can bus verilog design file
canbus
- 此例参照SJA1000CAN通信控制器，通过CAN总线控制器完成CAN总线的通信协议。所传文件为CAN总线的VERILOG代码。-This reference SJA1000CAN communication controller, to complete the communication protocol of CAN bus through the CAN bus controller. The transfer document for the CAN bus VERILOG code.
CAN-BUS-with-Verilog
- CAN 总线的verilog是实现与设计 很好的资料-implementation of can bus use verilog
can
- CAN总线控制器的FPGA源代码，verilog语言编写，支持CAN2.0B协议。对CAN总线开发者非常有用。-FPGA CAN bus controller source code, verilog language, support CAN2.0 protocol B. Developers of CAN bus is very useful.
CAN_verilog.tar
- CAN 2.0协议控制器，非常全面的控制器Verilog代码，可靠通信，可放心使用。(CAN Bus 2.0 Controller.)
CAN总线，I2C，USB等的FPGA实现源码
- 控制器局域网总线协议的Verilog代码(The Verilog code of the CAN bus protocol)