搜索资源列表
TCPClientEx
- 基于Win CE的TCP/IP通信源码,本例程完成了S3C2410的Win CE与PC机的Windows直接的TCP通信-Win CE based on the TCP/IP communication source, the routine was completed S3C2410 the Win CE and PC-Windows direct TCP communications
rs1_7seg_pci-0.0.1.tar
- Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd. -Raggedstone1 IP core.Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
AVR_Core
- AVR_Core IP CORE .VERY GOOD AS A STUDY FILE-AVR_Core IP CORE. VERY GOOD AS A STUDY FILE
Embedded_risc
- Embedded_risc IP CORE .VERY GOOD AS A STUDY FILE-Embedded_risc IP CORE. VERY GOOD AS A STUDY FILE
vhdl_source
- MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
GETIP
- getip1.cpp // // This program reports the IP address for each adapter in your machine. // To compile from command-line type: // // cl getip1.cpp wsock32.lib // // Make sure your INCLUDE and LIB environment variables are set up properly
BaselineJPEGSoftwareCodecCodes
- In term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three parts, and the goal of each part is described as follow. Part I: Design a baseli
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
AVR_Core8F.tar
- AVR IP core writen in VHDL. It is beta version, working even with AVR studio
cli_arm
- 基于嵌入式linux的命令行接口，实现了修改IP地址，MAC地址，网关等功能-cli based on embedded linux. realize functions of requiring ip address, mac address, gateway and etc.
IPsettingsandbacklight
- wince设置IP和背光样例代码，wince4.2，evc4.2编译，执行通过。-IP settings and backlight wince sample code, wince4.2, evc4.2 compiler, implementation through.
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
cyc2_cmon_080805
- Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
TCP_IP_Protocol
- TCP/IP协议栈在嵌入式系统中的应用，包括完整的代码-TCP/IP protocol stack in embedded system applications, including complete code
8051IP
- Standard 8051 IP Core
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
DM9000
- 嵌入式TCP/IP模块，内嵌web,可以配置成服务端或客户端，-LP based on the embedded TCP/IP modules, embedded web, can be configured into a server or client
myfifo
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_syn
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface