搜索资源列表
fifo88
- 8*8位的先入先出（fifo）数据缓冲器的vhdl源程序-8 * 8 of the first-in-first out (FIFO) buffers the data source VHDL
my_ramlib_06
- 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL descr iption, such as FIFO, Dual Port RAM, etc.
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
fifo_vhd
- vhdl编写的fifo程序-VHDL procedures prepared by the fifo
ramlib_06
- 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。
fifo_VHDL
- FIFO的源代码，详细描述FIFO的工作原理和过程，用VHDL编写。
video_fifo
- 有关视频方面的fifo设计,vhdl编写
fifo8_8
- 8*8位的fifo数据缓冲器的vhdl源程序。经过quartus ii 6.0 验证成功。
FIFO
- 用VHDL语言写的FIFO IDT7205驱动程序。时序仿真无误！-VHDL language used to write the FIFO IDT7205 driver. Timing simulation is correct!
proje2
- it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
fifo
- VHDL code for DATA PATH for performing A=A+3 and A=B+C TO DESIGN AND SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
VHDL-8bitFIFO
- FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它只的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等，本程序实现8位的FIFO功能,三位格雷码可表示8位的深度。-THE WIDTH of THE FIFO: namely information in English often see THE WIDTH, it is only a FIFO data read and write operations, as has 8 bit or 16 bit M
FIFO
- vhdl code for FIFO implementation
CCD_Array
- Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
fifo_FPGA
- 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)
Ethernet
- 简易以太网测试仪包含fifo缓冲模块，crc校验模块，检测和检测模块等(Simplified Ethernet Tester: including fifo modular, crc modular, check modular etc.)
fifo
- IL SAGIT D'UN FIFO EN DEscr iptION DE LANGUAGE vhdl
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
vhdl实现异步fifo
- 使用vhdl实现异步fifo功能，不占用ram资源，仅占用少量LE资源，且读写计数进行了格雷码转换，使用安全