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USB控制器VHDL程序
- USB控制器VHDL程（usb_xilinx_vhdl）,用XILINX公司的FPGA实现-VHDL-USB controller (usb_xilinx_vhdl) XILINX FPGA
实现USB接口功能的VHDL和verilog完整源代码
- 实现USB接口功能的VHDL和verilog完整源代码,Implementation USB interface functions of the VHDL and Verilog source code integrity
T2_USB_IN.rar
- usb芯片cy7c68013从fpga中读入数据的演示程序，verilog语言,CY7C68013 chip usb read from the FPGA into the data presentation process, verilog language
USB.rar
- 用VHDL实现的USB IP核，大家可以参考下,Use VHDL to achieve USB IP core, we can refer to the following
c8051
- USB v1.1 RTL and design specification
Usb
- 基于FPGA的驱动设计，使得用户的USB驱动在此完美实现。-FPGA-based drive design makes the user' s USB drive in this work perfectly.
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
altera
- USB-Blaster EEPROM的程序！-USB-Blaster EEPROM process!
usb_vhdl
- 一个USB 控制接口的参考设计，可作为USB设备的接口控制文件- a reference implement of the control interface of USB device
USB_kz
- 提供Cy7C68013 USB芯片开发源程序，由verilog编写-Cy7C68013 USB chip to provide the development of source code, prepared by the Verilog
DE2_demonstrations
- DE2开发板上的资料,主要是他的例子,含有各种接口程序,如VGA,USB,LCD等-DE2 development board information, mainly his example, contain a variety of interface program, such as VGA, USB, LCD, etc.
USB
- USB源代码，基于VHDL语言编写，在QuartusII上面已验证其功能-USB source code, based on the VHDL language, verified in QuartusII above its function
USB
- USB通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-USB communication protocol of the hardware descr iption language code for the FPGA bus interface controller development
usb-blaster
- quartus多种USB-bletera 自制下载线！
USB
- USB的VHDL实现源码（使用VHDL硬件描述语言，通过Altera QuartusII 开发）-USB to achieve the VHDL source code (using VHDL hardware descr iption language, through the development of Altera QuartusII)
USB
- Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be
USB
- 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
usb
- 这是一个USB的FPGA，VHDL研究解决方案，全部开源，详情请看内部txt文件-This is a USB-FPGA, VHDL on a solution, all open source, more information, please txt files inside
usb
- 程序说明: 本次实验控制开发板USB，与PC机进行通信，并在显示字符。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display char
USB
- USB CY7C68013 键盘发送 VHDL FPGA-USB CY7C68013 keypad VHDL FPGA