- RTP通用开发库(for Linux) linux环境下用纯c写的RTP协议的通用开发库
- ComponentArtWeb_UI_2006.1252.2006.2.0 ComponentArt Web.UI 2006.1252 for asp.net2.0
- JXC 进销存管理系统 进销存管理系统是一个典型的数据库开发应用程序
- FIBPlus.v6.9.5.forD5-2007.FS FIBPlus is a component suite intended for work with InterBase. It is direct
- LEACH.m
- 04505287 An increasing number of distributed generation units (DG units) are connected to the distribution network. These generators affect the operation and coordination of the distribution network protection. The influence from DG units that are coupled to the network with a power electronic converter (PEC) is different from that of conventional DG units with an electrical machine directly coupled to the network. This contribution shows that PEC
文件名称:usb_phy.tar
-
所属分类：
- 标签属性：
- 上传时间：2012-10-14
-
文件大小：7.21kb
-
已下载：1次
-
提 供 者：
-
相关连接：无下载说明：别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容来自于网络，使用问题请自行百度
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel
conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a
simplified UTMI interface. Currently doesn t do any error checking in
the RX section [should probably check for bit unstuffing errors].
Otherwise complete and fully functional.
There is currently no test bench available. This core is very simple
and is proven in hardware. I see no point of writing a test bench at
this time.
conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a
simplified UTMI interface. Currently doesn t do any error checking in
the RX section [should probably check for bit unstuffing errors].
Otherwise complete and fully functional.
There is currently no test bench available. This core is very simple
and is proven in hardware. I see no point of writing a test bench at
this time.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
usb_phy/
usb_phy/rtl/
usb_phy/rtl/verilog/
usb_phy/rtl/verilog/usb_tx_phy.v
usb_phy/rtl/verilog/CVS/
usb_phy/rtl/verilog/CVS/Repository
usb_phy/rtl/verilog/CVS/Entries
usb_phy/rtl/verilog/CVS/Root
usb_phy/rtl/verilog/usb_rx_phy.v
usb_phy/rtl/verilog/usb_phy.v
usb_phy/rtl/verilog/timescale.v
usb_phy/rtl/CVS/
usb_phy/rtl/CVS/Repository
usb_phy/rtl/CVS/Entries
usb_phy/rtl/CVS/Root
usb_phy/doc/
usb_phy/doc/README.txt
usb_phy/doc/CVS/
usb_phy/doc/CVS/Repository
usb_phy/doc/CVS/Entries
usb_phy/doc/CVS/Root
usb_phy/CVS/
usb_phy/CVS/Repository
usb_phy/CVS/Entries
usb_phy/CVS/Root
usb_phy/rtl/
usb_phy/rtl/verilog/
usb_phy/rtl/verilog/usb_tx_phy.v
usb_phy/rtl/verilog/CVS/
usb_phy/rtl/verilog/CVS/Repository
usb_phy/rtl/verilog/CVS/Entries
usb_phy/rtl/verilog/CVS/Root
usb_phy/rtl/verilog/usb_rx_phy.v
usb_phy/rtl/verilog/usb_phy.v
usb_phy/rtl/verilog/timescale.v
usb_phy/rtl/CVS/
usb_phy/rtl/CVS/Repository
usb_phy/rtl/CVS/Entries
usb_phy/rtl/CVS/Root
usb_phy/doc/
usb_phy/doc/README.txt
usb_phy/doc/CVS/
usb_phy/doc/CVS/Repository
usb_phy/doc/CVS/Entries
usb_phy/doc/CVS/Root
usb_phy/CVS/
usb_phy/CVS/Repository
usb_phy/CVS/Entries
usb_phy/CVS/Root
1999-2046 搜珍网 All Rights Reserved.
本站作为网络服务提供者，仅为网络服务对象提供信息存储空间，仅对用户上载内容的表现方式做保护处理，对上载内容本身不做任何修改或编辑。