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八位的伪随机数产生的verilog文件
- 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
Verilog-HDL
- 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子,这些例子全部通过了验证。第七章以后的设计实例,不仅有Verilog-HDL的例子,也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples w
sWave.rar
- 正弦波,Verilog波形发生器,很好的东西,Sine wave, Verilog waveform generator, a good thing
EPM240_SCH_and_program.rar
- EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器,ADC0804直流采样和显示,汉字滚动,交通灯,键盘,显示程序,计数器等等。,Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display pro
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
VGADIY
- 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
fcsr
- 伪随机序列产生器-代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ffcsr
- 伪随机序列产生器-filtered 代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
svc_timer33ms
- Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) co
signal
- verilog写的串口控制信号发生器,能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
viterbi
- Viterbi verilog generator
vhld_fpga_box
- Verilog 编写的波形发生器,可发生正弦波,三角波,方波,可以调频-Prepared Verilog waveform generator, can occur sine, triangle wave, square wave, you can FM
QIMO
- Verilog 编写的任意波形发生器,附带了顶层文件,输出波形-Verilog prepared arbitrary waveform generator, with a top-level document, the output waveform
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
waveform_-generator
- 简易信号波形发生器,可以产生四种波形,频率1k-20K步进可调。学习Verilog HDL的好例子。-imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL.
Verilog-hdlFPGA
- 关于FPGA的提高篇,Verilog HDL语言写的, 包含LCD控制VHDL程序与仿真,AD/DA,MASK,FSK,PSK,正弦波发生器,等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and VHDL simulation, AD/DA, MASK, FSK, PSK, sine wave generator, and so the classi
vim-verilog-generator
- Vim scr ipt for verilog coding and vidualisation. Some special features like useful syntaxis lighting included.
Verilog-dds
- 用Verilog实现的DDS,直接频率合成器,相位可调。-Verilog DDS generator
Clock generator
- A clock Generator in verilog
verilog状态机
- 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器,二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”,通过数码管显示出来;序列信号发生器的输出接入序列信号检测器,检测器检测当前的输入信号,若出现目标序列信号则通过蜂鸣器输出一个声响,表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, b