搜索资源列表
VHDL多功能时钟设计
- VHDL多功能时钟设计~~24小时制~带闹钟,VHDL design of multi-functional clock ~ ~ ~ 24 hours with alarm system
VHDL-ROM4.基于ROM的正弦波发生器的设计
- 基于ROM的正弦波发生器的设计:1.正弦发生器由波形数据存储模块(ROM),波形发生器控制模块及锁存模块组成 2.波形数据存储模块(ROM)定制数据宽度为8,地址宽度为6,可存储 64点正弦波形数据,用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 ,ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), wav
DS1307_LCD.通过IIC总线读写实时时钟DS1307
- 通过IIC总线读写实时时钟DS1307,并把时、分、秒显示在12864液晶屏上,用的CycloneII EP2C8,Quartus环境,Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
50M
- verilog 语言写的分频模块,实现用50Mhz的时钟频率分出1hz的频率,也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
vhdl
- 基于vhdl的数字时钟;24制,带有定时,闹钟等功能。-VHDL-based digital clock 24 system, with time, alarm clock functions.
clock
- 用verilog语言实现数字时钟,有注释,规范-Digital clock using verilog language, there are notes, specifications
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。 实验平台: 1. 一台PC机; 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
clock
- 数字钟设计,有分秒显示,上下午显示,可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
clock
- 用高速硬件语言VHDL设计的全功能数字钟,经测试运行稳定-VHDL language used high-speed hardware design full-function digital clock, tested and stable operation
clock
- 时钟的vhdl实现,具有打铃等功能,是一个很好的实现,我们做电子竞赛的源代码-VHDL clock to achieve a play-ling and other functions, is a good realization, we have the source code of the electronic competition
clock
- 基于VHDL的电子时钟设计-VHDL-based design of an electronic clock
clock
- 原创:基于VHDL语言编写的电子钟。采用模块化编写,可以调整时间,采用动态扫描显示时分秒-Original: Based on the VHDL language electronic bell. Modular prepared, you can adjust the time, dynamic scanning is displayed every minute
clock
- 可以实现时间调节,十二,二十四小时转换,定时,闹钟的时钟-Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
vhdl-digital-clock-design
- 设计一个具有特定功能的数字电子钟。准确计时,以数字形式显示h、min、s 的时间。小时的计时要求为二十四进位,分和秒的计时要求为六十进位。 该电子钟上电或按键复位后能自动显示系统提示00-00-00,进入时钟准备状态;第一次按电子钟功能键,电子钟从0时0分0秒开始运行,进入时钟运行状态;再次按电子钟功能键,则电子钟进入时钟调整状态,此时可利用各调整键调整时间,调整结束后可按功能键再次进入时钟运行状态。 -Designed with a specific function of a dig
alarm-clock
- 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
clock
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
clock
- 这是一个电子时钟的VHDL语言程序,非常好,注释也比较清晰,它包括电子时钟的所有功能。-This is an electronic clock VHDL language program, very good, the Notes are also clear, which includes all the features of the electronic clock.
clock
- VHDL数字闹钟实现,运用八位LED显示-VHDL realization of the digital alarm clock, the use of eight LED display
FPGA-clock
- 基于VHDL的时钟设计(de2开发平台),内含源代码,各模块的时序仿真图,结构原理图,以及完成报告。供大家参考学习。-VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
digital-clock-design
- VHDL语言编写的数字时钟设计程序,含源代码和波形仿真,还有顶层电路设计。-The VHDL language of the digital clock design procedures, including source code and the waveform simulation, but also the circuit design.