搜索资源列表
ARM-program
- ARM体系结构和编程,介绍ARM CPU 的细节，包括结构，寻址，指令集，汇编语言，cache管理，存储，函数调用参数传递，交叉编译连接及调试。-ARM architecture and programming on the ARM CPU details, including the structure, addressing, instruction set, assembly language, cache management, storage, transfer function ca
simplesim-3.0
- 一个很有名的硬件模拟器。可以模拟CPU，cache，以及内存等。支持多核处理器的模拟。
gems-release2.1.tar
- Wisconsin大学的gems项目工程源码，用于模拟CPU的cache，以及网络拓扑结构，和CPU乱序指令流。-Wisconsin University of gems Project source code, used to simulate the CPU' s cache, and network topology, and the CPU-of-order instruction stream.
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
mips
- 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
riscpu
- 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
Pccard
- pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB
mipsCPU
- MIPS CPU tested in Icarus Verilog
mipscpudesign
- cpu设计实例mips。MIPSI指令集32位CPU （1）MiniCore设计实例全32位操作，32个32位通用寄存器，所有指令和地址全为32位 （2）静态流水线（3～5级） （3）Forwarding技术 （4）片内L1 Cache，指令、数据各4KByte，硬件初始化 （5）没有TLB，但系统控制协处理器（CP0）具有除页面映射外的全部功能 -cpu design example mips. MIPSI instruction set 32-bit CPU (1)
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
w11_latest[1].tar
- 该项目包含一个完整的PDP - 11系统：一个内存管理单元七十○分之十一的CPU，但没有浮点单元，一组基本的单总线外围设备（DL11，LP11，PC11，RK11/RK05），以及最后但并非最不重要的一用于SRAM和PSRAM高速缓存和内存控制器。该设计的FPGA验证，目前运行Digilent的S3BOARD和NEXYS2板和靴子第5版的UNIX和2.11BSD UNIX操作系统。-The project contains a complete PDP-11 system: a 11/70 CP
tiny64_latest.tar
- Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also differnet word sizes. Due simpli
smdk2413_application_note_rev10
- SMDK2413 (Samsung MCU Development Kit) for S3C2413X is a platform that is suitable for code development of SAMSUNG s S3C2413X 16/32-bit RISC microcontroller (ARM926EJ-S) for hand-held devices and general applications. The S3C2413X consists of 16-/32-
CPUwithout-cache
- 5级流水无cache,CPU实验，是学习VHDL的好资料，对于了解CPU很有帮助！-5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!
cache.tar
- 一个CPU系统中LCACHE的设计，使用LRU算法替换-a LCACHE design in a CPU system, using arithmetic
code-water-no-cache
- 5级流水无cache的cpu代码，基于verilog，串行，两级流水-cpu code with no water nor cache