搜索资源列表
DCT
- 用于视频图像编码的8×8DCT变换，可用于MPEG4.H263等VHDL编程-For video images encoded 8 × 8DCT transform, can be used to MPEG4.H263 such as VHDL Programming
dct-code
- 离散余弦变换的VHDL实现，不错的代码和方法-Discrete cosine transform VHDL realization of good code and methods
jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
dct2
- 这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.
projekt
- Dct 2d in vhdl + descr iption -Dct 2d in vhdl+ descr iption
main_dct
- verilog code for dct
xapp610
- Verilog code for 2D-DCT with detailed documentation.
d1_dct
- FPGA 描述DCT ，希望对大家有用。-the DCT arithetics using fpga
123
- for DCT Image compression
1DCT_VHDL
- VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation
verilogdct
- dct实现verilog hdl的数字图像处理，源代码-dct achieve verilog hdl digital image processing, source code
Lab4b_24897141
- this is vhdl behavorial model of a dct chip at an algorithmic level
dctalgo
- vhdl coding for dct algorithm
addersubtractor10
- vhdl coding for adder subtractor used in dct
attachments_2010_01_29
- dct and idct vhdl code
ModelSim
- verilog Source code for DCT
DCT
- DCT / VHDL Discrete Cosine Transform
ch3_dct
- fpga dct变换，用以视频压缩和处理图像-fpga dct
DCT_IDCT
- verilog code for DCT and IDCT (JPEG)
dct
- JPEG Compression and Ethernet Communication on an FPGA