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dds
- dds的verilog实现 调用dds核 已经实验验证-dds 调用dds核
dds
- 基于Verilog HDL的DDS设计与仿真-Verilog HDL-based design and simulation of DDS
MY-DDS
- 利用altera公司的FPGA使用verilog语言实现DDS功能 外加DA 可将数字信号转换成标准正弦信号-Altera FPGA use verilog language of DDS functions plus DA converts digital signals into a standard sine signal
DDS-design-based-on-verilog
- 用verilog语言设计DDS数字频率合成器-DDS design based on verilog
dds
- 使用AD5559,结合quartus中的硬件描述语言,实现了雷达发射信号二相码信号-using AD9959 and combining with verilog to output a rada signal of Binary code
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star
DDS-SIN
- 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
DDS
- 基于verilog的DDS设计验证与仿真源代码，在quartus上实现，下载仿真成功-Based on the the the verilog DDS design verification and simulation of the source code, in quartus download simulation success
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
FPGA-DDS-algorithm
- 采用FPGA的DDS算法Verilog程序的实现-FPGA DDS algorithm Verilog program implementation
DDS
- 直接数字频率合成器dds，用verilog实现，经过quartus验证-Direct digital frequency synthesizer the dds, used verilog achieved after quartus verify
dds_mul
- 简单的多周期dds的verilog编程，出来一个正弦波，可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words
dds
- verilog编写的dds发生器，修改频率字可改频率-dds in verilog
DDS
- 用verilog语言实现，DDS信号发生与嵌入式逻辑分析仪的调用，程序功能完整 -Using verilog language, DDS signal generator with embedded logic analyzer called, the program features a complete
DDS
- FPGA产生DDS，未使用IP核，内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
verilog dds
- 用verilog 实现dds功能，可以实现方波，三角波等波形的输出
dds
- 在altera的FPGA上实现直接数字频率合成，即用verilog实现DDS，输出正弦波形，在modelsim软件中仿真通过，已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code
DDS
- 用Verilog HDL 编写的一个最基本的DDS程序，发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
DDS
- Verilog HDL实现FPGA的DDS功能，含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures