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sixiangzaibosheji
- 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70M
DDS_sine
- DDS扫频信号源的FPGA实现，有的是verilog编写，欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
123_ise9migration
- DDS正弦信号发生器verilog的功能强大很实用-dds sin verilog
dds1
- 用ALTERA 公司的fpga芯片，编程语言是VerilogHDL,实现DDS数字信号发生器，可以产生正弦信号，三角信号，矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal
da--sine
- 利用dds方法，通过DA输出正弦波，频率1KHz 频率根据代码可调-DA output sine wave frequency 1KHz (Verilog)
verilog_sine-wave-generator
- verilog语言书写的基于DDS相频累加器的正弦波发生器-verilog language of the sine wave generator
sin_generate
- verilog 实现 dds正弦 函数信号发生器 verilog 实现 dds正弦 函数信号发生器-verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
verilog_dds
- verilog实现dds，用于FPGA产生正弦波，适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
address_gen
- 基于FPGA使用Verilog语言构成的DDS信号发生器-DDS signal generator based on FPGA using Verilog language constitutes
LSY_wave
- 比赛时写的李萨如波形发生器的代码，用verilog写的，里面集成数据采集和DDS波形发生。-Game when writing the the Lissajous waveform generator code, written in verilog the inside integrated data acquisition and DDS waveform generation.
Regtangle_wave_DDS
- 利用VERILOG编写的DDS产生方波的程序-Using VERILOG written DDS program produce a square wave
Sender
- 直序扩频通信发送部分的源代码，用verilog编的，包括信源模块、扩频模块、极性变换模块和DDS调制模块-Direct sequence spread spectrum communication sent part of the source code, compiled with verilog source modules, spread spectrum modules, polarity transform module and DDS modulation module
ad9850
- 介绍了用FPGA控制DDS产生任意频率范围之内的可调制正弦波，13位BPSK,ASK等。控制字由串口写入。-verilog control AD9850 to get psk ask
No.2DDS
- 用Verilog HDL实现DDS信号发生器。-DDS signal generator using Verilog HDL.
5-15
- 用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特-Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits
signal-generator
- Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation -DDS signal generator circuit design, Verilog source code, can be directly used, simulation
dds_work
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件--verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
DDS_dac9764
- verilog语言编写的DDS信号源，采用DAC9764-verilog DDS signal source language, using DAC9764
dds_double_new
- FPGA用verilog语言编写的 dds程序，两路输出，频率可调，相位可调，输出波形可调-FPGA using verilog language dds program, two outputs, adjustable frequency, phase adjustable, adjustable output waveform
DDS_Ad9854_Verilog
- DDS控制模块 AD9854 VERILOG-DDS control module AD9854 VERILOG