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CIC_deci4.rar
- cic抽取滤波器ip核,用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter,used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
myfir
- 利用fir滤波器ip-core设计滤波器,数据为16bit,速率为61.44mhz,工作时钟为245.76mhz-The use of fir filter ip-core design of filters, the data for the 16bit, rate 61.44mhz, working clock 245.76mhz
BPSK
- 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制,其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
CIC32
- cic滤波器,没有用ip核,用vhdl语言写的32倍抽取,4阶,经过验证-cic filter, did not use ip core, the language used to write 32 times vhdl extract, 4 bands, proven
signal-fir
- FPGA实现FIR滤波器,对信号的滤波处理,其中I用IP核实现数据的存储核-Based on the IP core of FPG, realize FIR filter design
fir_test01
- 在quartus ii 环境下,用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时,消耗资源太大的时候,需要自己编写滤波器的源代码,这里给出我们常用的串行FIR核的verilog语言代码设计文件,并通过作者时序仿真验证,并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
FIR
- FPGA设计在设计过程中使用ISE软件自带的IP核时,消耗资源太大的时候,需要自己编写滤波器的源代码,这里给出我们常用的串行FIR核的verilog语言代码设计文件,并通过作者时序仿真验证,并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
qam16-TX
- 基于Altera MAX10 FPGA的QAM16发送端设计代码,其中采用了MAX10 Fir滤波器IP核。供相关设计人员参考,或者进一步咨询本人。-Based on Altera MAX10 FPGA design of QAM16 the sender code, which uses the MAX10 Fir filter IP core. Related reference for designers, or further consultation himself.
Verilog-IIC-read-MPU6050-Filter
- 本代码实现了读MPU6050 三轴6个数据,用其中的GY和AZ、AX结合融合滤波算法,解出X单轴角度,并在黑金开发板的EP4C15F17C8芯片上调试成功,±5°范围内LED灯灭,左右摆动时相应左右灯亮。 顶层模块每隔5ms,发出一个is_read高电平,下面的模块读取一次数据,并计算,更新LED状态。有关计算都用的ip核,占用资源很大。希望对小小小小白有所帮助。 -Verilog codes read 6 axis data of MPU6050, and use GY AZ AX w
E4_4_IIR4Functions
- 用verilog语言实现的一个IIR滤波器,因为现在的ise等工具中没有包含相关的ip核,所以需要手动设计。 -With verilog language to achieve an IIR filter, because now ise and other tools do not contain the relevant ip kernel, so the need for manual design.
E4_1_fir1
- 基于ip核的fir滤波器设计,调用了ip核,并实例化,对初学者很有用。-Based on the ip kernel fir filter design, call the ip kernel, and instantiation, very useful for beginners.
dfe_filter
- DEF算法的FIR滤波器verilog代码,内有乘法器IP核,可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
iir_2n_ip_float_demo
- 使用altera提供的ip核,实现了浮点数运算的2阶iir滤波器,结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
FIR设计实现sgh
- FIR滤波FPGA实现 ,已在仿真软件上验证实现,不是IP核,不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)