搜索资源列表
mips-simple
- Mips veriloge code with its results
MIPS-processor-Verilog-code
- 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instruct
at91sam7s64-MIPS-WinARM-1_21
- at91sam7x mips driver
mips-VHDL
- 自己作业代码，应用VHDL语言实现一个多周期的简单MIPS核-AlphaJob code, the application of VHDL language more than one cycle of a simple MIPS core
mips
- this code is the simulator of mips processor which is written in C++. this simulator handles the standard ISA of MIPS and can be a good assignment for computer architecture
mips-verilog
- verilog mips documet will show you about mips
MIPS-multi-cycle-(Quarters-II--Verillig)
- Multi cycle MIPS processor verilog
MIPS-CPU
- 全指令集MIPS-CPU工程，包含各分模块工程、测试程序和详细设计文档，QuartusII7.2测试通过。-MIPS-CPU works full instruction set, contains the sub-module engineering, testing procedures and detailed design documents, QuartusII7.2, the test passes.
MIPS
- 简单的MIPS流水线实现，无相关处理。实现R指令，J指令或者I指令。-Simple MIPS pipelined related processing. To achieve the R command, directive, or I instruction.
mips.linux.inter
- Mips Linux 中断异常源代码分析-Mips Linux source code analysis interrupt exception
MIPS-and-CPU-design-and-simulation
- 兼容MIPS指令集的CPU设计与仿真 处理器架构为多周期，指令用32为字长（取指占一个周期），4k的存储器（指令存储器和数据存储器分开），IO与存储器统一编制，能支持20条指令以上-MIPS instruction set compatible CPU design and simulation
MIPS
- 基于VHDL的百万指令处理器（MIPS）设计。-A descr iption of MIPS based on VHDL
MIPS-CPU
- 完整的32位MIPS处理器工程，拥有整个工程和doc文件说明-Full 32-bit MIPS processor works with the entire project and doc file descr iption
MIPS
- 研究生课程 ： 简易MIPS核的systemc实现代码-Graduate courses: Simple MIPS core implementation code based on SystemC
mips
- 基于MIPS架构实现的单周期处理器，包含多种基本操作，验证方法是把自己的学号写进连续内存。-MIPS-based architecture for single-cycle processor, includes a variety of basic operations, authentication method is to learn their numbers written contiguous memory.
MIPS
- 用verilog编写的简单的类MIPS多周期流水化处理器实现，基本功能包括9条指令和两位动态分支预测，压缩包里的word详细说明了结构中的细节-Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies th
MIPS-AND-arm-VXWORKS-BSP-CODE-SOURCE
- mips arm vxworks 源码 BSP -MIPS AND arm VXWORKS BSP CODE SOURCE.zip
MIPS
- 5个stage的pipeline MIPS，支持着JUMP，BRANCH等跳转命令。-simple 5-stages MIPS structure which supports forwarding commands.
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
mips
- 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips