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pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
MIPS
- 组成原理大作业--基于MIPS的运算器设计,内附详细设计文档,包含设计文档和使用手册,主程序,测试程序,还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条,用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
PipeLine.tar Verilog实现MIPS五段流水线
- Verilog实现MIPS五段流水线,22条指令(基本算术、移位和load、store指令),模块化设计,含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
CPU
- verilog编写CPU: 1. 哈佛存储器结构,大端格式; 2. 类MIPS精简指令集,支持子程序调用和软中断; 3. 实现了乘除法; 4. 五级流水线,工作频率可达80MHz(每个时钟周期一条指令,不计流水线冲突)。 -MIPS like CPU using verilog
MIPS
- MIPS处理器的组员大作业,可以直接运行,提交,环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII
mipsCPU
- MIPS CPU tested in Icarus Verilog
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档,台湾一个大学生的MIPS CPU完整设计文档,内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
vhdl-MIPS
- Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
mips
- 实现了一个简单的微处理器的功能,l里面有累加器,加法器,寄存器-adgfdhgjjj jdhjhgdkhgjhgjhgkjhgkgkh
mips
- 使用verilog設計的MIPS處理器,mips處理機的模擬且可合成驗証-MIPS processor using the verilog design, mips processor synthesis of analog and can be verified
mlite.tar
- 很强大的mips处理器,用verilog实现的-A very strong mips processor implemented using verilog
mips
- MIPs CPU,VERILOG代码,经过QUARTUS综合,时序分析,验证无误。-MIPS CPU
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
mips
- mips pipeline code.. copyright material for fr-mips pipeline code.. copyright material for free
mips-cpu
- 单周期的mips处理器设计,用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
Pipelined-MIPS
- MIPS架构5级流水线设计,支持常用的整数指令。-5-stage pipeline MIPS architecture designed to support common integer instructions.
mips
- mips verilog进行编写cpu,其中包括了若干的基本指令(use the verilog language to programme the CPU)
mips-cpu-master
- MIPS Implementation in Verilog. Full source code!