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MIPS
- 组成原理大作业--基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
MIPS
- mips处理器指令仿真器，可查看流水线执行方式-mips instruction processor emulator, you can review the pipeline implementation
mipscpudesign
- cpu设计实例mips。MIPSI指令集32位CPU （1）MiniCore设计实例全32位操作，32个32位通用寄存器，所有指令和地址全为32位 （2）静态流水线（3～5级） （3）Forwarding技术 （4）片内L1 Cache，指令、数据各4KByte，硬件初始化 （5）没有TLB，但系统控制协处理器（CP0）具有除页面映射外的全部功能 -cpu design example mips. MIPSI instruction set 32-bit CPU (1)
mips-iv
- MIPS IV Instruction Set,详细讲解了mips iv的指令系统-MIPS IV Instruction Set, detailed account of the instruction set mips iv
mipssingelcycle
- mips single cycle implementation five files auxiliary pc data memory instruction memory adder forwarding
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
mips-iv
- MIPS 指令集，比see mips 更适合用作手册使用-This appendix describes the instruction set architecture (ISA) for the central processing unit (CPU) in the MIPS IV architecture. The CPU architecture defines the non-privileged instructions that execute in user mode.
Tomasulo
- Implementation of the Tomasulo Algorithm using the MIPS instruction Set
CU
- mips指令控制器。fpga上板验证实现。为cpu课设重要模块-mips instruction controller.
CPUsourcecode
- 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly use
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
08-MIPS-arithmetic.pdf
- dsp processor mips instruction implementation plan-dsp processor mips instruction implementation plan
see-mips-run-
- mips处理器的计算机体系结构，mips指令与C语言之间的转换-mips processor computer architecture, mips instruction and C language conversion between
CPU
- 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft int
ALU
- 11条指令MIPS指令系统CPU中的ALU设计-11 instruction in the MIPS instruction ALU design in the system CPU
CPU_design
- 微机原理32位微处理器设计。可以完成基本的MIPS指令。-Microcomputer Principle 32 of the microprocessor design. You can complete the basic MIPS instruction.
MIPS-CPU
- 全指令集MIPS-CPU工程，包含各分模块工程、测试程序和详细设计文档，QuartusII7.2测试通过。-MIPS-CPU works full instruction set, contains the sub-module engineering, testing procedures and detailed design documents, QuartusII7.2, the test passes.
MIPS-and-CPU-design-and-simulation
- 兼容MIPS指令集的CPU设计与仿真 处理器架构为多周期，指令用32为字长（取指占一个周期），4k的存储器（指令存储器和数据存储器分开），IO与存储器统一编制，能支持20条指令以上-MIPS instruction set compatible CPU design and simulation
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction