搜索资源列表
iir_16
- 用QUARTUS软件实现一个16阶的IIR滤波器-QUARTUS software with a 16-order IIR filter
verilog-vga
- Verilgo编写的VGA显示接口示例程序, 在显示器上显示矩形彩条, 包含Quartus II 8.1工程文件及VGA的相当资料(PDF及WORD文档)-Verilgo prepared VGA display interface sample program, the color of the rectangle on the display, including the Quartus II 8.1 project file and VGA considerable data (PDF a
Verilog-Design
- 包括三个文档: 1.基于Altera Quartus II 的模块化设计应用 2.基于Xilinx ISE的的模块化设计示例 3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for desi
cordic
- 在QUARTUS环境下，通过Verilog实现cordic，产生sin，cos-In QUARTUS environment, through the Verilog implementation cordic, generate sin, cos
LCD12864
- LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
2BCD
- 二进制转BCD码 verilog hdl Quartus II 9.0sp2 编译通过 所有的文件-Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
I2C
- 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language:
DAC
- Quartus 9.0 Project of a dual DAC0808 interface.Very simple and clean design, plus Avalon slave interface!
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
SynplifyPro_Quartus_v5_v4_1
- Quartus仿真软件SynplifyPro应用指导-Guidance on the application simulation software SynplifyPro Quartus
quartus10.0-crack
- quartus10.0破解文件#用于Quartus II 10.0 ： #将sys_cpt.dll覆盖掉安装目录即可。 #把license.dat里的XXXXXXXXXXXX 用您老的网卡号替换(在Quartus II 10的Tools菜单下选择License Setup，下面就有NIC ID)。 #在Quartus II 10的Tools菜单下选择License Setup，然后选择License file，最后点击OK。 #注意：license文件存放
eetop.cn_Crack_Altera_6.0-9.1
- quartus中的DSP Builder6.0到 9.0 的全部破解绝对实用。-quartus 9.0 in all DSP Builder6.0 to break the absolute practical.
spi
- SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
Quartus-9.0-books
- Quartus 9.0 tt_nios2_hardware_tutorial, embeded_handbook, n2cpu_nii72v1_HRDWR_REF, n2cpu_nii72v3_EMBD_PRFR, n2sw_nii72v2_SOFTWR_DEV, ug_nios2_getting_started
TEST5
- 8位硬件加法器设计 熟悉Quartus II的VHDL文本设计流程全过程，学习简单时序电路的设计、仿真和测试。-eight bit Hardware adder design Familiar with Quartus II VHDL text design flow process, learn the simple sequential circuits design, simulation and testing
Crack_QII_10.1_Windows
- quartus 10.1破解文件 内部人员用-quartus 10.1 crack file with internal staff
serial_adder
- This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
quartus
- 本代码利用SOPC实现走马灯功能，在QUARTUS9.0，NIOSII9.0环境下开发。-Using SOPC implementation of the code features a revolving door in QUARTUS9.0, NIOSII9.0 development environment.
SRAM
- Verilog 语言描述，SRAM的实验操作，Quartus中编译通过-Verilog language descr iption, SRAM experimental operation, Quartus compiled by
Quartus
- Quartus的鉴相器硬件电路设计 Quartus的鉴相器硬件电路设计 -Quartus the hardware design phase detector phase Quartus' s Quartus hardware circuit design of hardware circuit design phase