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  1. I2CIP

    0下载:
  2. IIC的IP.这是经过验证的源代码,而且还有IIC的说明文档,很实用。-IIC IP. This is the result of verification of source code, but also the documentation, IIC, very practical.
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:650.24kb
    • 提供者:诸葛飞
  1. SATA_Verification_IP-SystemVerilog

    1下载:
  2. SATA Verification IP - SystemVerilog,是使用FPGA做的sata接口部分,是一篇文档-SATA Verification IP- SystemVerilog, is to use FPGA to do sata interface part, is a document
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:394.42kb
    • 提供者:
  1. DW8051(Verilog)

    0下载:
  2. 51单片机IP核源码,可以在fpga实现,并进行仿真与验证-51 single-chip IP nuclear source, you can achieve the fpga, and simulation and verification
  3. 所属分类:SCM

    • 发布日期:2017-03-30
    • 文件大小:66.46kb
    • 提供者:xuhuifeng
  1. RealizationofdigitaldownconversionbyFPGA

    0下载:
  2. 介绍在FPGA 器件上如何实现单通道数字下变频(DDC)系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the prepa
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:159.01kb
    • 提供者:于银
  1. baseonVHDL

    0下载:
  2. 基于VHDL语言的8051IP核的设计与验证研究 是一篇我从通过学校校内IP下载的论文,觉得挺好-VHDL-8051IP-based design and verification of nuclear research is an IP I downloaded from the school through the school paper, I feel quite good
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-19
    • 文件大小:5.01mb
    • 提供者:shintar
  1. UARTipcore

    0下载:
  2. 这是一个关于UART的IP核,用VHDL写的。经过本人的鉴证,非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:21.76kb
    • 提供者:11
  1. MC8051

    0下载:
  2. 摘要:分析了与标准8051 MCU 兼容的MC8051 IP 核结构原理与设计层次,详细论述了MC8051 IP 核的FPGA 实现与 应用方法。通过试验验证,其性能比标准8051 MCU 高,方便与系统其他模块的集成。在各种嵌入式系统和片上系统 中使用该IP 核具有重要意义。 关键词: 单片机; MC8051; IP 核; FPGA; VHDL-Abstract: This paper is compatible with standard 8051 MCU MC8051 IP c
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:331.37kb
    • 提供者:xing
  1. spi_vip

    0下载:
  2. This Verification IP from syswip I tested in one of my project its working fine-This is Verification IP from syswip I tested in one of my project its working fine
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:226.12kb
    • 提供者:shobhit
  1. Fnstrucervisor

    0下载:
  2. 基于IP复用的片上级系统的构建与验证Film based on IP reuse and verification of system construction supervisor-Film based on IP reuse and verification of system construction supervisor
  3. 所属分类:Embeded-SCM Develop

    • 发布日期:2017-03-31
    • 文件大小:588.37kb
    • 提供者:linux163
  1. pli_socket_example_pc

    0下载:
  2. vpi/pli socket example code-co-verification using TCP/IP socket (hardware model : verilog+ vpi as server) (software as a client)
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:25.59kb
    • 提供者:samuel chuang
  1. huawei_verification

    1下载:
  2. 华为内部资料--利用 IP Workbench结合 SystemC构建复杂芯片系统验证平台-Huawei internal information- using IP Workbench chip system with SystemC verification platforms to build complex
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:392.11kb
    • 提供者:syf
  1. ug_avalon_verification

    0下载:
  2. Avalon Verification IP Suite verification userguide
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:22.77kb
    • 提供者:aravind
  1. ipI2C

    0下载:
  2. IP核的设计与验证,使用I2C进行FPGA与FPGA之间进行通信-Design and verification of IP cores, using I2C communication between the FPGA and the FPGA. .
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1.05mb
    • 提供者:逸风
  1. usb

    0下载:
  2. USB的verilog IP模块,经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:56.46kb
    • 提供者:sj
  1. DE0_NANO_SDRAM_Nios_Test

    0下载:
  2. SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
  3. 所属分类:VHDL编程

  1. DE0_NANO_SDRAM_Nios_Test

    0下载:
  2. SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
  3. 所属分类:VHDL编程

  1. aurora_bram

    0下载:
  2. Xilinx SP605评估板 Aurora IP(GTP 简单协议) 核功能验证 调试源代码 chipscope验证通过-Xilinx SP605 Evaluation Kit Aurora IP core functional verification debugging source code and chipscope verified
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:2.97mb
    • 提供者:
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