文件名称:DE0_NANO_SDRAM_Nios_Test
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- 上传时间：2014-07-18
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文件大小：2mb
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SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is used to access a SDRAM, and how the Nios II processor is used to read and write the SDRAM for hardware verification. The SDRAM controller handles the complex aspects of using SDRAM by initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals.
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压缩包 : DE0_NANO_SDRAM_Nios_Test.zip 列表 .qsys_edit/filters.xml .qsys_edit/preferences.xml DE0_NANO_QSYS/synthesis/DE0_NANO_QSYS.qip DE0_NANO_QSYS/synthesis/DE0_NANO_QSYS.v DE0_NANO_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v DE0_NANO_QSYS/synthesis/submodules/altera_avalon_st_clock_crosser.v DE0_NANO_QSYS/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v DE0_NANO_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v DE0_NANO_QSYS/synthesis/submodules/altera_merlin_address_alignment.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_burst_adapter.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_master_agent.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_master_translator.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv DE0_NANO_QSYS/synthesis/submodules/altera_merlin_width_adapter.sv DE0_NANO_QSYS/synthesis/submodules/altera_reset_controller.sdc DE0_NANO_QSYS/synthesis/submodules/altera_reset_controller.v DE0_NANO_QSYS/synthesis/submodules/altera_reset_synchronizer.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_addr_router.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_addr_router_001.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_altpll.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_cmd_xbar_demux.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_cmd_xbar_demux_001.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_cmd_xbar_mux.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_id_router.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_id_router_001.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_id_router_002.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_id_router_006.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_irq_mapper.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_jtag_uart.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_key.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys.ocp DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys.sdc DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_bht_ram.mif DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_dc_tag_ram.mif DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_ic_tag_ram.mif DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_jtag_debug_module_sysclk.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_jtag_debug_module_tck.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_jtag_debug_module_wrapper.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_mult_cell.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_ociram_default_contents.mif DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_oci_test_bench.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_rf_ram_a.mif DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_rf_ram_b.mif DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_nios2_qsys_test_bench.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_onchip_memory2.hex DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_onchip_memory2.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_rsp_xbar_demux.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_rsp_xbar_demux_002.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_rsp_xbar_mux.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_rsp_xbar_mux_001.sv DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_sdram.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_sdram_test_component.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_sysid_qsys.v DE0_NANO_QSYS/synthesis/submodules/DE0_NANO_QSYS_timer.v DE0_NANO_QSYS.bsf DE0_NANO_QSYS.cmp DE0_NANO_QSYS.html DE0_NANO_QSYS.qsys DE0_NANO_QSYS.sopcinfo DE0_NANO_SDRAM_Nios_Test.done DE0_NANO_SDRAM_Nios_Test.fit.smsg DE0_NANO_SDRAM_Nios_Test.fit.summary DE0_NANO_SDRAM_Nios_Test.jdi DE0_NANO_SDRAM_Nios_Test.map.smsg DE0_NANO_SDRAM_Nios_Test.map.summary DE0_NANO_SDRAM_Nios_Test.pin DE0_NANO_SDRAM_Nios_Test.qpf DE0_NANO_SDRAM_Nios_Test.qsf DE0_NANO_SDRAM_Nios_Test.qws DE0_NANO_SDRAM_Nios_Test.sdc DE0_NANO_SDRAM_Nios_Test.sof DE0_NANO_SDRAM_Nios_Test.sta.summary DE0_NANO_SDRAM_Nios_Test.v DE0_NANO_SDRAM_Nios_Test_assignment_defaults.qdf demo_batch/DE0_NANO_SDRAM_Nios_Test.bat demo_batch/DE0_NANO_SDRAM_Nios_Test.elf demo_batch/DE0_NANO_SDRAM_Nios_Test.sh demo_batch/DE0_NANO_SDRAM_Nios_Test.sof PLLJ_PLLSPE_INFO.txt software/.metadata/.lock software/.metadata/.log software/.metadata/.mylyn/contexts/ software/.metadata/.mylyn/repositories.xml.zip software/.metadata/.plugins/org.eclipse.cdt.core/.log software/.metadata/.plugins/org.eclipse.cdt.core/DE0_NANO_SDRAM_Nios_Test.1380261928373.pdom software/.metadata/.plugins/org.eclipse.cdt.core/DE0_NANO_SDRAM_Nios_Test_bsp.1380261919531.pdom software/.metadata/.plugins/org.eclipse.cdt.make.core/.log software/.metadata/.plugins/org.eclipse.cdt
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