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Thermometer
- thermometer vhdl project
Greedy_Snake_verilog
- 基于FPGA的verilog代码，在Spartan3开发板上实现了传统贪吃蛇的游戏，通过VGA显示在屏幕上。按键控制方向。-This is a FPGA project, which used verilog and implemented the traditional game of Greedy Snake.
clock
- vhdl 数字钟工程文件夹 解压就可以用 quartus ii工程文件 -vhdl digital clock project folder can be used to extract the project file quartus ii
a-vhdl-can-controller
- a vhdl can controller project using vhdl programmming language-a vhdl can controller project using vhdl programmming language..
all-digital-fm-receiver
- all digital fm receiver using vhdl programming language project for electronics and communication engineering students.
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
POC-Project
- 系统总线与打印机之间的借口：并行输出控制器POC的设计。涉及POC与CPU，POC与printer之间的握手操作。-Between the system bus and an excuse for the printer: parallel output controller POC design. Involved in POC and CPU, POC and the printer handshake between the operations.
A-VHDL-Primer---Bhasker
- VHDL exaples project from CPLD or FPGA
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
40716003-VHDL
- What is VHDL? • VHDL stands for VHSIC Hardware Descr iption Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
carry-ripple
- carry ripple adder code (whole project) in vhdl using xilinx tool. VHD file has source code
VHDL-example
- VHDL的几个实用例程，能帮助开发工程的同学更好的完成项目。-Several practical VHDL routines to help students develop a better project to complete the project.
zkrMtr
- 1 button counter vhdl project
XSA-P2MOUSE
- simple ps2 mouse vhdl project
XSA-PS2KBD
- ps2 keyboard vhdl project
led-decoder
- 7 segment display decoder vhdl project
doc
- BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional
ControlWD
- 汽车尾灯控制器，用VHDL编写的。包括仿真。是一个完整工程-Car taillight controller, written by VHDL. Including simulation. Is a complete project