搜索资源列表
7led
- 7段发光二极管vhdl程序，可以验证led的fpga验证程序-seven of the light-emitting diode VHDL procedures can verify they simply led to the certification process
buzz
- 一个用vhdl语言编成的可以让蜂鸣器发声的的程序。-with a monument of the VHDL language allows the buzzer of the procedure.
clockbyvhdl
- 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
pwmvhdl
- 一个在xilinx的ise环境下编译仿真成功的pWM程序。-one of the Xilinx environment ideally compiler pWM success of the simulation procedures.
keybyise
- 一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。-a company embarks on the environment and ideally compile successful simulation keyboard operations.
8051core-Verilog
- 8051的源代码-8051 source code
VERcf_fft_1024_8
- 1024点８位FFT的Verilog语言实现-1024-point FFT eight Verilog language
ddr_verilog_xilinx
- 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
jfq1
- vhdl和verling hdl 的加法器-VHDL and the Adder.
watch2
- vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
20060412183015974
- 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
traffic_light
- 一个用verilog编写的模拟交通灯控制的源代码。模拟在十字路口的双向交通灯。-a prepared using Verilog simulation of traffic lights to control the source code. Simulation at the crossroads of two-way traffic lights.
scu_all_fpga
- 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
clockv
- 使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.-use Verilog language prepared by the digital clock procedures. Schools are slow, quick school, alarm clock functions.
1.i2c_slave
- I2C的slave端程序,用于响应master端,并进行通信-the slave I2C software, in response to the master terminal, and communications
sericommu
- 串口通信程序.在波特率为9600的串口通信程序-serial communication program. The baud rate for the 9600 serial communication program
digitalinterfaceuart
- 文件说明了在fpga/cpld中怎样实现数据接口及其实例了urat-note of the document they simply / cpld How Data Interface and the examples of urat
wavegenerator_testbench
- 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
ARM9_instruction_cache_verilogCodes
- Arm9指令Cache缓存模块的verilog代码，对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
song123
- 梁祝音乐设计 hdl语言实现 很常用-love music HDL design language is used