搜索资源列表
ddr_sdram_controller_vhdl
- ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
i2c_slave_model_verilog
- 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.
mt48lc8m16a2
- sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
trellis_verlog
- ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
div5_verilog
- 5分代码及说明，verilog代码，几乎所有的IC面试都会问到这个问题，所以总结了一下发了上来，共同学习！-5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!
adma
- Wishbone dma ip core
FPGApro
- VERILOG HDL 实际工控项目源码 开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2
ps2_soc2
- PS2的源代码VHDL语言实现，可以和计算机直接连接．做鼠标键盘接口．-PS2 source VHDL, and can be connected directly to the computer. So the mouse, keyboard interface.
tenbench
- 硬件描述语言,verilog HDL,实现了解码器的设计-hardware descr iption language, verilog HDL, the decoding of Design
counter1
- vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧-vhdl counter source, we see it vhdl counter source, we see it
Uart_TR
- Verilog编写的简单异步串口 完全原创，站长请查看内容-Verilog prepared by the simple asynchronous serial completely original, the station can be accessed content
news5f
- Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
SPtransform
- Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
IICforsopcbuilder
- IIC控制器 for Sopc Builder-IIC controller for Sopc Builder
mod6_divide
- 用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
de_mux
- 一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
key_prog
- 简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.-easy-to-read 4 * 4 keyboard and display program. To the preparation of other forms of keyboard scan procedures are certain guiding significance.
alu_32_bit
- verilog 32-bit ALU-verilog 32-bit ALU
SPI_verilogHDL
- 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success