搜索资源列表
UART_rec
- verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功 和大家一起分享！^_^
recuart_50m
- 利用VHDL实现CPLD（EPM240T100C5）的串口接收程序
串口通信收发模块
- verilog编写的串口通信的接收模块和发送模块，经过仿真有效
uart_rxd
- 基于verilog hdl的UART串口接收子程序。-Verilog hdl a UART-based serial port to receive subroutine.
my_uart_top
- 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and recei
senduard_50m
- 串口发送: 使用串口发送程序接收二进制码（9600波特率） ，用拨码开关控制发送二进制的高四位，按板上的第二个按钮，LED灯会相应的亮起，PC 会收到相应的数据-Serial port to send: Use the serial port to send a program to receive a binary code (9600 baud), with DIP switch control to send binary high-4, according to board the
uart_receive
- 串口接收数据44个8bit数据，并且将4个8bit数拼接成32bit数，存进ram中， 可以通过 in system memory editro 查看-Serial port receive data 44 8bit data, and will be spliced into four 8bit number of 32bit number, deposit into the ram in, you can see in system memory editro
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
FPGA_sata_receiver
- 基于EasyFPGA030的串口接收显示设计。-Serial receiver based EasyFPGA030 display design.
urat232
- 串口程序，FPGA实现，可以实现简单的发送和接收-Serial process, FPGA implementation, you can send and receive simple
uart
- vhdl语言的串口发送/接收模块，本人用在多个工程，很好用。-vhdl language of the serial transmit/receive module, I used a number of projects, very good use.
smg_interface
- FIFO高速数据采集处理，串口发送接收封装，独立于上一模块，-FIFO high-speed data acquisition and processing, sending and receiving serial package, independent of the previous module,
UART-Altera
- 使用Atera FPGA CycloneII 实现串口通信，遵循RS232协议。FPGA上的模块实现了数据的接收，取补码和发送。(Achieve serial communication with FPGA, following the protocol of RS232.)
用串口DMA方式接收发送数据
- 在STM32板子与电脑串口助手进行通信,用串口的DMA方式,先接收,再发送到PC端,可以连续接收,通过按键一次发送.(In the STM32 board and computer serial assistant for communication, using the serial port DMA way, first receive, and then sent to the PC terminal, you can receive continuously, sent through
parameter_uart_rx
- 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data wi
uart
- 实现串口发送和接收功能，数据处理模块可自行修改。(Serial port to send and receive functions, data processing module can modify its own.)
urat接收程序
- uart串口接收程序，实现基于Rs232传输线的数据的接收。(UART serial receiving program to realize data receiving based on Rs232 transmission line.)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
sci_host
- fpga实现高速多路同步串口，接收发送模块(Implementation of high-speed multi-channel synchronous serial port by FPGA)
串口接收程序
- 异步串口接收程序，主要功能是将异步串口转换成8位并口数据，数据格式为8位数据、1个停止位、1个停止位、无校验位，可以自行设置波特率。